Product manual

Secure Digital (SD) Card Protocol Description

Table 4-15. R6 Response

Bit Position 47 46 [45:40] [39:8] Argument Field [7:1] 0

Width (bits) 1 1 6 16 16 7 1

Value ‘0’ ‘0’ x x x x ‘1’

Description start bit transmission bit Command

index

(‘000011’)

New published RCA

[31:16] of the card

[15:0] card status bits:

23,22,19,12:0

(see Table 4-28)

CRC7 end bit

4.11. Timings

All timing diagrams use the schematics and abbreviations listed in Table 4-16.

Table 4-16. Timing Diagram Symbols

S Start Bit (= 0)

T Transmitter Bit (Host = 1, Card = 0)

P One-cycle Pull-up (= 1)

E End Bit (=1)

Z High Impedance State (-> = 1)

D Data Bits

X Don’t Care Data Bits (from Card)

* Repeater

CRC Cyclic Redundancy Check Bits (7 Bits)

Card Active

Host Active

The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card respectively host

output driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors R

CMD

respectively R

DAT

Actively-driven P-bits are less sensitive to noise. All timing values are defined in Table 4-17.

4.11.1. Command and Response

Both host command and card responses are clocked out with the rising edge of the host clock.

Card identification and card operation conditions timing

The timing for CMD2 and ACMD41 is given bellow. The command is followed by a period of two Z bits (allowing

time for direction switching on the bus) and then by P bits pushed up by the responding card. The card response to

the host command starts after N

clock cycles.