User Manual

Secure Digital (SD) Bus Protocol Description
TriFlash with SD Interface Product Manual (Preliminary), Rev. 1.2 © 2002/2003 SANDISK CORPORATION
4-15
1) CLK
CMD
2) CLK
CMD
100KHz-400KHz Clocks
Polling less than 50ms interval
1st
1st
2nd
2nd
3rd
3rd
<50ms
<50ms
(ACMD41)
(ACMD41)
Figure 4-9. Host Procedures Waiting for Device to be Ready
• It is an obvious requirement that the clock must be running for the TriFlash to output data or response
tokens. After the last SD Bus transaction, the host is required to provide eight (8) clock cycles for the
device to complete the operation before shutting down the clock. Following is a list of various SD Bus
transactions:
− A command with no response—eight clocks after the host command end bit.
− A command with response—eight clocks after the device response end bit.
− A read data transaction—eight clocks after the end bit of the last data block.
− A write data transaction—eight clocks after the CRC status token.
• The host is allowed to shut down the clock of a “busy” device. The TriFlash will complete the
programming operation regardless of the host clock. However, the host must provide a clock edge for
the device to turn off its busy signal. Without a clock edge the TriFlash (unless previously
disconnected by a deselect command -CMD7) will force the DAT0 line down, permanently.
4.6. Cyclic Redundancy Codes (CRC)
The Cyclic Redundancy Check (CRC) is intended for protecting TriFlash commands, responses and data transfer
against transmission errors on the SD Bus. One CRC is generated for every command and checked for every
response on the CMD line. For data blocks, CRC is generated for each DAT line per transferred block. The CRC is
generated and checked as described in the following:
CRC7
The CRC7 check is used for all commands, for all responses except type R3, and for the CSD and CID registers.
The CRC7 is a 7-bit value and is computed as follows:
generator polynomial: G(x) = x
7
+ x
3
+ 1.
M(x) = (first bit) * x
n
+ (second bit) * x
n-1
+...+ (last bit) * x
0
CRC[6...0] = Remainder [(M(x) * x
7
) / G(x)]
The first bit is the most significant bit of the corresponding bit string (of the command, response, CID or CSD). The
degree n of the polynomial is the number of CRC protected bits decreased by one. The number of bits to be
protected is 40 for commands and responses (n = 39), and 120 for the CSD and CID (n = 119).