User Manual

TriFlash Interface Description

3-5

DAT 0-3

CLK

TriFlash

Host

CMD

DAT

Figure 3-3. SD Bus Circuitry Diagram

DAT

and R

CMD

are pull-up resistors protecting the CMD and the DAT line against bus floating when all device

drivers are in a hi-impedance mode. Refer to Table 3-5 for the component values and conditions. C1, C2 and C3 are

the equivalent load capacitance (CL) of each line in the bus.

3.3. SPI Bus Topology

The TriFlash SPI interface is compatible with SPI hosts available on the market. As with any other SPI device the

TriFlash SPI channel consists of the following 4 signals:

• CS—Host to device Chip Select signal.

• CLK—Host to device clock signal

• DataIn—Host to device data signal.

• DataOut—Device to host data signal.

Another SPI common characteristic, which is implemented in the TriFlash as well, is byte transfers. All data tokens

are multiples of 8 bit bytes and always byte aligned to the CS signal.

The SPI standard defines the physical link only and not the complete data transfer protocol. In SPI Bus mode, the

TriFlash uses a subset of the SD protocol and command set.

The TriFlash identification and addressing algorithms are replaced by a hardware Chip Select (CS) signal. A device

(slave) is selected, for every command, by asserting (active low) the CS signal (see Figure 3-4).

The CS signal must be continuously active for the duration of the SPI transaction (command, response and data).

The only exception is device programming time. At this time the host can de-assert the CS signal without affecting

the programming process.

The bi-directional CMD and DAT lines are replaced by uni-directional DataIn and DataOut signals. This eliminates

the ability of executing commands while data is being read or written. An exception is the multi read/write

operations. The Stop Transmission command can be sent during data read. In the multi block write operation a Stop

Transmission token is sent as the first byte of the data block.