Product manual

There are a few restrictions the SPI host must follow:

• The bus frequency can be changed at any time (under the restrictions of maximum data transfer

frequency, defined by the miniSD Cards).

• It is an obvious requirement that the clock must be running for the miniSD Card to output data or

response tokens. After the last SPI bus transaction, the host is required to provide 8 (eight) clock

cycles for the card to complete the operation before shutting down the clock. Throughout this 8-clock

period, the state of the CS signal is irrelevant. It can be asserted or de-asserted. Following is a list of

the various SPI bus transactions:

− A command/response sequence. Eight clocks after the card response end bit. The CS signal can be

asserted or de-asserted during these 8 clocks.

− A read data transaction. Eight clocks after the end bit of the last data block.

− A write data transaction. Eight clocks after the CRC status token.

• The host is allowed to shut down the clock of a “busy” card. The miniSD Card will complete the

programming operation regardless of the host clock. However, the host must provide a clock edge for

the card to turn off its busy signal. Without a clock edge, the miniSD Card (unless previously

disconnected by de-asserting the CS signal) will force the dataOut line down, permanently.

5.1.9. Error Conditions

The following sections provide valuable information on error conditions.

5.1.9.1. CRC and Illegal Commands

Unlike the miniSD Card protocol, in SPI mode the card will always respond to a command. The response indicates

acceptance or rejection of the command. A command may be rejected in any one of the following cases:

• It is sent while the card is in read operation (except CMD12 which is legal).

• It is sent while the card is in Busy.

• Card is locked and it is other than Class 0 or 7 commands.

• It is not supported (illegal opcode).

• CRC check failed.

• It contains an illegal operand.

• It was out of sequence during an erase sequence.

Note that in case the host sends command while the card sends data in read operation then the response with an

illegal command indication may disturb the data transfer.

5.1.9.2. Read, Write and Erase Time-out Conditions

The times after which a time-out condition for read operations occur are (card independent) either 100 times longer

than the typical access times for these operations given below or 100ms. The times after which a time-out condition

for Write/Erase operations occur are (card independent) either 100 times longer than the typical program times for

these operations given below or 250ms. A card shall complete the command within this time period, or give up and

return an error message. If the host does not get any response with the given time out it should assume the card is

not going to respond anymore and try to recover (e.g., reset the card, power cycle, reject). The typical access and

program times are defined in the following sections.