Service manual

Circuit Description

3-24

PPD( 7: 0)

nAUTOFD

nSTROBE

BUSY

BYTE0

BYTE1

COMM

AND

BYTE

DATA BYTE

12345 6

1. The host places data on the data lines and indicates a data cycle by setting nAUTOFD

2. Host asserts nSTROBE low to indicate valid data

3. Peripheral acknowledhes host by setting BUSY high

4. Host sets nSTROBE high. This is the edge that should be used to clock the data into the Peripheral

5. Peripheral sets BUSY low to indicate that it is ready for the next byte

6. The cycle repeats, but this time it is a command cycle because nAUTOFD is low

PPD

(7:0)

BUSY

nACK

nAUTOFD

BYTE0

BYTE1

COMMAND BYTE

DATA BYTE

12 3 4 56

nINIT

<ECP Hardware Handshaking Timing (forward)

1. The host request a reverse channel transfer by setting nINIT low

2. The peripheral signals that it is OK to proceed by setting PE low

3. The peripheral places data on the data lines and indicates a data cycle by setting BUSY high

4. Peripheral asserts nACK low to indicate valid data

5. Host acknow ledges by setting nAUTOFD high

6. Peipheral sets nACK high. This is the edge that should be used to clock the data into the host

7. Host sets nAUTOFD low to indicate that it is ready for the next byte

8. The cycle repeats, but this time it is a command cycle because BUSY is low