Service manual

Circuit Description
3-16
3-2-5-1 SDRAM DRAM read timing
Basically the Extended Data Out DRAM is similar to Fast Page Mode DRAM. For FPM, the data are valid only
when the nCAS is active while reading the internal data, however, it has a latch that the data will be
continuously outputted even after the nCAS is inactivated.
While configuring the software, you must set the timing register of SFR considering the clock speed and the
DRAM spec.
* Note : 1. CS can be don’t cared when RAS, CAS and WE are hih at the clock high going dege.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the
same.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
HIGH
Row Active
(A-Bank)
Read
(A-Bank)
Read
(C-Bank)
Precharge
(B-Bank)
Read
(D-Bank)
: Don't care
Row Active
(B-Bank)
*Note 2
*Note 1
Row Acive
(C-Bank)
Read
(B-Bank)
Precharge
(A-Bank)
(D-Bank)
Precharge
(C-Bank)
Precharge
(D-Bank)
BA 0
BA 1
A 10 /AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
RAa RBb RCc RDd
RAa RBb CAa RCc CBb RDd CCc CDd