Service manual

Circuit Description

3-15

3-2-5 DRAM CONTROL

1) DEVICE

2) OPERATING PRINCIPLE

DRAM can either read or write. The data can be stored in the DRAM only when the power is on. It stores

data white the CPU processes data. The address to read and write the data is speciﬁed by RAS SIGNAL

and CAS SIGNAL. DRAMWE*SIGNAL is activated when writing data and DRAMOE*SIGNAL, when read-

ing. You can expand up to 64MBYTE of DRAM in this system.

TYPE NO.

K4S

CAPACITY

16MBYTES (1M * 16BITS * 4Bank * 2)

Start Address ~ End Address Contents

0x00000000 ~ 0x00FFFFFF ROM Bank0

0x01000000 ~ 0x01FFFFFF ROM Bank1

0x02000000 ~ 0x02FFFFFF ROM Bank2

0x03000000 ~ 0x03FFFFFF ROM Bank3

0x04000000 ~ 0x0FFFFFFF Unused

0x10000000 ~ 0x1FFFFFFF Special Function Registers

0x20000000 ~ 0x20FFFFFF I/O Bank0

0x21000000 ~ 0x21FFFFFF I/O Bank1

0x22000000 ~ 0x22FFFFFF I/O Bank2

0x23000000 ~ 0x23FFFFFF I/O Bank3

0x24000000 ~ 0x24FFFFFF I/O Bank4

0x25000000 ~ 0x25FFFFFF I/O Bank5

0x26000000 ~ 0x26FFFFFF DMA I/O Bank0

0x27000000 ~ 0x27FFFFFF DMA I/O Bank1

0x28000000 ~ 0x28FFFFFF DMA I/O Bank2

0x29800000 ~ 0x29FFFFFF DMA I/O Bank3

0x2A000000 ~ 0x2FFFFFFF Unused

0x30000000 ~ 0x30FFFFFF RSH SRAM

0x31000000 ~ 0x31FFFFFF HPVC SRAM

0x32000000 ~ 0x32FFFFFF MOTOR SRAM

0x33000000 ~ 0x37FFFFFF Unused

0x38000000 ~ 0x38FFFFFF USB CSR & FIFO

0x39000000 ~ 0x390003FF USB PLUG DETECT

0x38000500 ~ 0x3FFFFFFF Unused

0x40000000 ~ 0x4FFFFFFF SDRAM array0 (bank 0)

0x50000000 ~ 0x5FFFFFFF SDRAM array1 (bank 1)

0x60000000 ~ 0x6FFFFFFF SDRAM array2 (bank 2)

0x70000000 ~ 0x7FFFFFFF SDRAM array3 (bank 3)

0x80000000 ~ 0xBFFFFFFF SDRAM array0~4 (Mirror)

0xC0000000 ~ 0xC00007FF MAC

0xC0000800 ~ 0xC0FFFFFF Unused