Service manual

Circuit Description
3-9
2) RISC MICROCESSOR PIN & INTERFACE(CIP4)
No Pin Name I/O Description Pad Type Current drive
1 GND2 P Vss Supply vss2i -
2 NTEST I Nand Tree Test Mode Selection pticd -
3 TM I Global Test Mode Selection pticd -
4 TEST1 I Test Mode Selection 1 pticd -
5 GND17 P Vss Supply vss3op -
6 TEST2 I Test Mode Selection 2 pticd -
7 XDACK1 I DMA Acknowledge Signal 1 ptis -
8 XDREQ1 O DMA Request Signal 1 phob4 4mA
9 VDD1 P Vdd Supply vdd2i -
10 XDACK2 I DMA Acknowledge Signal 2 ptis -
11 XDREQ2 O DMA Request Signal 2 phob4 4mA
12 XDACK3 I DMA Acknowledge Signal 3 ptis -
13 XDREQ3 O DMA Request Signal 3 phob4 4mA
14 nRESET I Global Reset ptis -
15 CLK_OUT O PLL Clock Out phob12 12mA
16 GND3 P Vss Supply vss2i -
17 XP I Clock Oscillation Input phsoscm26 10~40MHz
18 XPOUT O Clock Oscillation Output phsoscm26 10~40MHz
19 GNDD16 P Vss Supply vss2t_abb -
20 FILTER* O PLL Filter Pump Out poar50_abb -
21 GND1 P Vss Supply vbb_abb -
22 VDDA9,VDDD9 P Vdd Supply vdd2t_abb -
23 GND24,GND33 P Vss Supply vss3t_abb -
24 RTC_XO O RTC Clock Oscillation Output poar50_abb -
25 RTC_XI I RTC Clock Oscillation Input piar50_abb -
26 VDD8,VDD18 P Vdd Supply vdd3t_abb -
27 IRQ O Interrupt Request Signal phob4 4mA
28 nCS I CIP4 Chip Select ptis -
29 GND4 P Vss Supply vss2i -
30 nRD I CIP4 CPU Read Control ptis -
31 nWR I CIP4 CPU Write Control ptis -
32 BA1 I Bank Address Bus [1] ptis -
33 BA0 I Bank Address Bus [0] ptis -
34 GND19 P Vss Supply vss3op -
35 A5 I CPU Address Bus [5] ptis -
36 A4 I CPU Address Bus [4] ptis -
37 A3 I CPU Address Bus [3] ptis -
38 VDD2 P Vdd Supply vdd2i -
39 A2 I CPU Address Bus [2] ptis -
40 A1 I CPU Address Bus [1] ptis -
41 A0 I CPU Address Bus [0] ptis -
42 GND5 P Vss Supply vss2i -
43 D31 B CPU Data Bus [31] phbst8 8mA