Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 89
Figure 78. Test Access Port Timing Diagram
Figure 79. TRST
Timing Diagram
Table 56. SJC Timing Parameters
ID Parameter
All Frequencies
Unit
Min Max
SJ1 TCK cycle time 100
1
—ns
SJ2 TCK clock pulse width measured at
V
M
2
40 — ns
SJ3 TCK rise and fall times — 3 ns
SJ4 Boundary scan input data set-up time 10 — ns
SJ5 Boundary scan input data hold time 50 — ns
SJ6 TCK low to output data valid — 50 ns
SJ7 TCK low to output high impedance — 50 ns
SJ8 TMS, TDI data set-up time 10 — ns
SJ9 TMS, TDI data hold time 50 — ns
SJ10 TCK low to TDO data valid — 44 ns
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
TDO
(Output)
VIH
VIL
Input Data Valid
Output Data Valid
Output Data Valid
TMS
SJ8 SJ9
SJ10
SJ11
SJ10
TCK
(Input)
TRST
(Input)
SJ13
SJ12