Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
88 Freescale Semiconductor
Electrical Characteristics
4.3.21 SJC Electrical Specifications
This section details the electrical characteristics for the SJC module. Figure 76 depicts the SJC test clock
input timing. Figure 77 depicts the SJC boundary scan timing, Figure 78 depicts the SJC test access port,
Figure 79 depicts the SJC TRST timing, and Table 56 lists the SJC timing parameters.
Figure 76. Test Clock Input Timing Diagram
Figure 77. Boundary Scan (JTAG) Timing Diagram
TCK
(Input)
VM
VM
VIH
VIL
SJ1
SJ2
SJ2
SJ3
SJ3
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
Data
Outputs
VIH
VIL
Input Data Valid
Output Data Valid
Output Data Valid
SJ4
SJ5
SJ6
SJ7
SJ6