Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
86 Freescale Semiconductor
Electrical Characteristics
Figure 73. Internal-Reset Card Reset Sequence
4.3.20.2.2 Cards with Active Low Reset
The sequence of reset for this kind of card is as follows (see Figure 74):
1. After powerup, the clock signal is enabled on CLK (time T0)
2. After 200 clock cycles, RX must be high.
3. RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on
RX during those 40000 clock cycles)
4. RST is set High (time T1)
5. RST must remain High for at least 40000 clock cycles after T1 and a response must be received
on RX between 400 and 40000 clock cycles after T1.
Figure 74. Active-Low-Reset Card Reset Sequence
SVEN
CLK
RX
2
T0
1
response
2
1
< 200 clock cycles
< 40000 clock cycles400 clock cycles <
SVEN
CLK
RX
2
T0
1
response
RST
T1
1
2
< 200 clock cycles
< 40000 clock cycles400 clock cycles <
3
3
3
400000 clock cycles <