Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
78 Freescale Semiconductor
Electrical Characteristics
The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD,
DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD,
DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the
DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers.
4.3.16 Memory Stick Host Controller (MSHC)
Figure 65, Figure 66, and Figure 67 depict the MSHC timings, and Table 49 and Table 50 list the timing
parameters.
Figure 65. MSHC_CLK Timing Diagram
Figure 66. Transfer Operation Timing Diagram (Serial)
tSCLKwh
tSCLKwl
tSCLKc
tSCLKr tSCLKf
MSHC_SCLK
tSCLKc
MSHC_SCLK
tBSsu tBSh
tDsu tDh
MSHC_BS
MSHC_DATA
(Output)
tDd
MSHC_DATA
(Intput)