Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 75
Figure 63 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is
added. When a burst is transmitted within single active chip select interval, the RS can be changed at
boundaries of words.
Figure 63. 5-Wire Serial Interface (Type 2) Timing Diagram
Preamble
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
RW
Output data
D7 D6 D5 D4 D3 D2 D1 D0
DISPB_SD_D
(Output)
(Input)
Preamble
DISPB_D#_CS
DISPB_SD_D_CLK
DISPB_SD_D
RW
Input data
DISPB_SD_D
D7 D6 D5 D4 D3 D2 D1 D0
(Output)
(Input)
Write
Read
DISPB_SER_RS
DISPB_SER_RS
1 display IF
clock cycle
1 display IF
clock cycle
1 display IF
clock cycle
1 display IF
clock cycle
1 display IF
clock cycle
1 display IF
clock cycle