Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 71
IP36 Controls hold time for write Tdchw Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw — ns
IP37 Slave device data delay
8
Tracc 0 — Tdrp
9
–Tlbd
10
–Tdicur–1.5 ns
IP38 Slave device data hold time
8
Troh Tdrp–Tlbd–Tdicdr+1.5 — Tdicpr–Tdicdr–1.5 ns
IP39 Write data setup time Tds Tdicdw–1.5 Tdicdw — ns
IP40 Write data hold time Tdh Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw — ns
IP41 Read period
2
Tdicpr Tdicpr–1.5 Tdicpr Tdicpr+1.5 ns
IP42 Write period
3
Tdicpw Tdicpw–1.5 Tdicpw Tdicpw+1.5 ns
IP43 Read down time
4
Tdicdr Tdicdr–1.5 Tdicdr Tdicdr+1.5 ns
IP44 Read up time
5
Tdicur Tdicur–1.5 Tdicur Tdicur+1.5 ns
IP45 Write down time
6
Tdicdw Tdicdw–1.5 Tdicdw Tdicdw+1.5 ns
IP46 Write up time
7
Tdicuw Tdicuw–1.5 Tdicuw Tdicuw+1.5 ns
IP47 Read time point
9
Tdrp Tdrp–1.5 Tdrp Tdrp+1.5 ns
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These
conditions may be device specific.
2
Display interface clock period value for read:
3
Display interface clock period value for write:
4
Display interface clock down time for read:
5
Display interface clock up time for read:
6
Display interface clock down time for write:
7
Display interface clock up time for write:
8
This parameter is a requirement to the display connected to the IPU
9
Data read point
10
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific.
Table 47. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)
ID Parameter Symbol Min. Typ.
1
Max. Units
Tdicpr T
HSP_CLK
ceil⋅
DISP#_IF_CLK_PER_RD
HSP_CLK_PERIOD
----------------------------------------------------------------
=
Tdicpw T
HSP_CLK
ceil⋅
DISP#_IF_CLK_PER_WR
HSP_CLK_PERIOD
------------------------------------------------------------------
=
Tdicdr
1
2
---
T
HSP_CLK
ceil
2 DISP#_IF_CLK_DOWN_RD⋅
HSP_CLK_PERIOD
-------------------------------------------------------------------------------
⋅=
Tdicur
1
2
---
T
HSP_CLK
ceil
2 DISP#_IF_CLK_UP_RD⋅
HSP_CLK_PERIOD
--------------------------------------------------------------------
⋅=
Tdicdw
1
2
---
T
HSP_CLK
ceil
2 DISP#_IF_CLK_DOWN_WR⋅
HSP_CLK_PERIOD
---------------------------------------------------------------------------------
⋅=
Tdicuw
1
2
---
T
HSP_CLK
ceil
2 DISP#_IF_CLK_UP_WR⋅
HSP_CLK_PERIOD
----------------------------------------------------------------------
⋅=
Tdrp T
HSP_CLK
ceil
DISP#_READ_EN
HSP_CLK_PERIOD
--------------------------------------------------
⋅=