Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
70 Freescale Semiconductor
Electrical Characteristics
Figure 59. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram
Table 47. Asynchronous Parallel Interface Timing Parameters—Access Level
ID Parameter Symbol Min. Typ.
1
Max. Units
IP27 Read system cycle time Tcycr Tdicpr–1.5 Tdicpr
2
Tdicpr+1.5 ns
IP28 Write system cycle time Tcycw Tdicpw–1.5 Tdicpw
3
Tdicpw+1.5 ns
IP29 Read low pulse width Trl Tdicdr–Tdicur–1.5 Tdicdr
4
–Tdicur
5
Tdicdr–Tdicur+1.5 ns
IP30 Read high pulse width Trh Tdicpr–Tdicdr+Tdicur–1.5 Tdicpr–Tdicdr+
Tdicur
Tdicpr–Tdicdr+Tdicur+1.5 ns
IP31 Write low pulse width Twl Tdicdw–Tdicuw–1.5 Tdicdw
6
–Tdicuw
7
Tdicdw–Tdicuw+1.5 ns
IP32 Write high pulse width Twh Tdicpw–Tdicdw+
Tdicuw–1.5
Tdicpw–Tdicdw+
Tdicuw
Tdicpw–Tdicdw+
Tdicuw+1.5
ns
IP33 Controls setup time for read Tdcsr Tdicur–1.5 Tdicur — ns
IP34 Controls hold time for read Tdchr Tdicpr–Tdicdr–1.5 Tdicpr–Tdicdr — ns
IP35 Controls setup time for write Tdcsw Tdicuw–1.5 Tdicuw — ns
IP28, IP27
Read Data
IP32, IP30
IP37
IP38
DISPB_PAR_RS
DISPB_DATA
DISPB_DATA
DISPB_WR
(Input)
(Output)
IP35,IP33
IP36, IP34
IP31, IP29
IP40
IP39
IP45, IP43
IP42, IP41
DISPB_RD (ENABLE_L)
DISPB_D#_CS
(READ/WRITE)
DISPB_DATA[17]
(ENABLE_H)
read point
IP46,IP44
IP47