Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
66 Freescale Semiconductor
Electrical Characteristics
Figure 55. Parallel Interface Timing Diagram—Read Wait States
4.3.15.5.2 Parallel Interfaces, Electrical Characteristics
Figure 56, Figure 58, Figure 57, and Figure 59 depict timing of asynchronous parallel interfaces based on
the system 80 and system 68k interfaces. Table 47 lists the timing parameters at display access level. All
timing images are based on active low control signals (signals polarity is controlled via the
DI_DISP_SIG_POL Register).
WRITE OPERATION READ OPERATION
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISPB_DATA
DISP0_RD_WAIT_ST=00
DISP0_RD_WAIT_ST=01
DISP0_RD_WAIT_ST=10