Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
64 Freescale Semiconductor
Electrical Characteristics
Figure 53. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram
DISPB_D#_CS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_D#_CS
DISPB_WR
DISPB_RD
DISPB_DATA
(READ/WRITE)
(ENABLE)
DISPB_PAR_RS
DISPB_PAR_RS
(READ/WRITE)
(ENABLE)
(READ/WRITE)
(ENABLE)
Burst access mode with sampling by CS signal
Burst access mode with sampling by separate burst clock (BCLK)
Single access mode (all control signals are not active for one display interface clock after each display access)