Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 63
Figure 52. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by WR/RD signals
Burst access mode with sampling by separate burst clock (BCLK)
Single access mode (all control signals are not active for one display interface clock after each display access)