Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 59
4.3.15.4 Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are
identical to parameters of the synchronous interface. See Section 4.3.15.2.2, “Interface to Active Matrix
TFT LCD Panels, Electrical Characteristics” on page 55.
4.3.15.4.1
Interface to a TV Encoder, Functional Description
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits
D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 50 depicts the
interface timing,
• The frequency of the clock DISPB_D3_CLK is 27 MHz (within 10%).
• The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.
• The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal.
It remains low for a single clock cycle.
• The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC
signal. It remains low for at least one clock cycle.
— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC
and DISPB_D3_HSYNC coincide.
— At a transition to an even field (of the same frame), they do not coincide.
• The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC
signal being high.
Table 46. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
ID Parameter Symbol Value Units
IP21 SPL rise time Tsplr (BGXP – 1) * Tdpcp ns
IP22 CLS rise time Tclsr CLS_RISE_DELAY * Tdpcp ns
IP23 CLS fall time Tclsf CLS_FALL_DELAY * Tdpcp ns
IP24 CLS rise and PS fall time Tpsf PS_FALL_DELAY * Tdpcp ns
IP25 PS rise time Tpsr PS_RISE_DELAY * Tdpcp ns
IP26 REV toggle time Trev REV_TOGGLE_DELAY * Tdpcp ns