Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
58 Freescale Semiconductor
Electrical Characteristics
4.3.15.3 Interface to Sharp HR-TFT Panels
Figure 49 depicts the Sharp HR-TFT panel interface timing, and Table 46 lists the timing parameters. The
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics,” on page 55.
The timing images correspond to straight polarity of the Sharp signals.
Figure 49. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
3
Display interface clock up time
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Tdicu
1
2
---
T
HSP_CLK
ceil
2 DISP3_IF_CLK_UP_WR⋅
HSP_CLK_PERIOD
----------------------------------------------------------------------
⋅=
D1 D2
DISPB_D3_CLK
DISPB_D3_DATA
DISPB_D3_SPL
DISPB_D3_HSYNC
DISPB_D3_CLS
DISPB_D3_PS
DISPB_D3_REV
1 DISPB_D3_CLK period
IP26
D320
Horizontal timing
IP22
IP23
IP25
IP21
IP24
Example is drawn with FW+1=320 pixel/line, FH+1=240 lines.
SPL pulse width is fixed and aligned to the first data of the line.
REV toggles every HSYNC period.