Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 57
NOTE
HSP_CLK is the High-Speed Port Clock, which is the input to the Image
Processing Unit (IPU). Its frequency is controlled by the Clock Control
Module (CCM) settings. The HSP_CLK frequency must be greater than or
equal to the AHB clock frequency.
The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and
V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF,
SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA
channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters
are programmed via the DI_DISP3_TIME_CONF, DI_HSP_CLK_PER and DI_DISP_ACC_CC
Registers.
Figure 48 depicts the synchronous display interface timing for access level, and Table 45 lists the timing
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
Figure 48. Synchronous Display Interface Timing Diagram—Access Level
Table 45. Synchronous Display Interface Timing Parameters—Access Level
ID Parameter Symbol Min Typ
1
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These
conditions may be device specific.
Max Units
IP16 Display interface clock low time Tckl Tdicd–Tdicu–1.5 Tdicd
2
–Tdicu
3
2
Display interface clock down time
Tdicd–Tdicu+1.5 ns
IP17 Display interface clock high
time
Tckh Tdicp–Tdicd+Tdicu–1.5 Tdicp–Tdicd+Tdicu Tdicp–Tdicd+Tdicu+1.5 ns
IP18 Data setup time Tdsu Tdicd–3.5 Tdicu — ns
IP19 Data holdup time Tdhd Tdicp–Tdicd–3.5 Tdicp–Tdicu — ns
IP20 Control signals setup time to
display interface clock
Tcsu Tdicd–3.5 Tdicu — ns
IP19
DISPB_D3_CLK
DISPB_DATA
IP18
IP20
DISPB_D3_VSYNC
IP17IP16
DISPB_D3_DRDY
DISPB_D3_HSYNC
other controls
Tdicd
1
2
---
T
HSP_CLK
ceil
2 DISP3_IF_CLK_DOWN_WR⋅
HSP_CLK_PERIOD
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