Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
56 Freescale Semiconductor
Electrical Characteristics
Figure 47. TFT Panels Timing Diagram—Vertical Sync Pulse
Table 44 shows timing parameters of signals presented in Figure 46 and Figure 47.
Table 44. Synchronous Display Interface Timing Parameters—Pixel Level
ID Parameter Symbol Value Units
IP5 Display interface clock period Tdicp Tdicp
1
1
Display interface clock period immediate value.
Display interface clock period average value.
ns
IP6 Display pixel clock period Tdpcp (DISP3_IF_CLK_CNT_D+1) * Tdicp ns
IP7 Screen width Tsw (SCREEN_WIDTH+1) * Tdpcp ns
IP8 HSYNC width Thsw (H_SYNC_WIDTH+1) * Tdpcp ns
IP9 Horizontal blank interval 1 Thbi1 BGXP * Tdpcp ns
IP10 Horizontal blank interval 2 Thbi2 (SCREEN_WIDTH – BGXP – FW) * Tdpcp ns
IP11 HSYNC delay Thsd H_SYNC_DELAY * Tdpcp ns
IP12 Screen height Tsh (SCREEN_HEIGHT+1) * Tsw ns
IP13 VSYNC width Tvsw if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH+1) * Tdpcp
else
(V_SYNC_WIDTH+1) * Tsw
ns
IP14 Vertical blank interval 1 Tvbi1 BGYP * Tsw ns
IP15 Vertical blank interval 2 Tvbi2 (SCREEN_HEIGHT – BGYP – FH) * Tsw ns
IP14
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
Start of frame
End of frame
IP12
IP15
IP13
IP11
Tdicp
T
HSP_CLK
DISP3_IF_CLK_PER_WR
HSP_CLK_PERIOD
------------------------------------------------------------------
⋅ for integer
DISP3_IF_CLK_PER_WR
HSP_CLK_PERIOD
------------------------------------------------------------------
,
T
HSP_CLK
floor
DISP3_IF_CLK_PER_WR
HSP_CLK_PERIOD
------------------------------------------------------------------
0.5 0.5±+
⎝⎠
⎛⎞
⋅ for fractional
DISP3_IF_CLK_PER_WR
HSP_CLK_PERIOD
------------------------------------------------------------------
,
⎩
⎪
⎪
⎨
⎪
⎪
⎧
=
Tdicp T
HSP_CLK
DISP3_IF_CLK_PER_WR
HSP_CLK_PERIOD
------------------------------------------------------------------
⋅=