Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 55
• DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted onto the display. When disabled, the data is invalid and the trace is off.
Figure 45. Interface Timing Diagram for TFT (Active Matrix) Panels
4.3.15.2.2 Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 46 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC
and DISPB_D3_DRDY signals.
Figure 46. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 47 depicts the vertical timing (timing of one frame). All figure parameters shown are
programmable.
DISPB_D3_CLK
123 mm-1
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_HSYNC
LINE 1
LINE 2 LINE 3 LINE 4 LINE n-1 LINE n
DISPB_D3_DRDY
DISPB_D3_DATA
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_DATA
DISPB_D3_CLK
IP7
IP9
IP10
IP8
Start of line
IP5
IP6