Technical data

Electrical Characteristics

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3

Freescale Semiconductor 47

Figure 37. Mobile DDR SDRAM Write Cycle Timing Diagram

NOTE

SDRAM CLK and DQS related parameters are being measured from the

50% point—that is, high is defined as 50% of signal value and low is

defined as 50% of signal value.

NOTE

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 35 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

Table 35. Mobile DDR SDRAM Write Cycle Timing Parameters

Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.

ID Parameter Symbol Min Max Unit

SD17 DQ & DQM setup time to DQS tDS 0.95 — ns

SD18 DQ & DQM hold time to DQS tDH 0.95 — ns

SD19 Write cycle DQS falling edge to SDCLK output delay time. tDSS 1.8 — ns

SD20 Write cycle DQS falling edge to SDCLK output hold time. tDSH 1.8 — ns

SDCLK

DQS (output)

DQ (output)

DQM (output)

Data Data

Data Data Data Data

SD17

SD18

SD19

SD20