Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
46 Freescale Semiconductor
Electrical Characteristics
Figure 36. SDRAM Self-Refresh Cycle Timing Diagram
NOTE
The clock will continue to run unless both CKEs are low. Then the clock
will be stopped in low state.
Table 34. SDRAM Self-Refresh Cycle Timing Parameters
ID Parameter Symbol Min Max Unit
SD16 CKE output delay time tCKS 1.8 — ns
SDCLK
CS
CAS
RAS
ADDR
BA
WE
CKE
Don’t care
SD16
SD16