Technical data

Electrical Characteristics

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3

Freescale Semiconductor 45

NOTE

SDR SDRAM CLK parameters are being measured from the 50%

point—that is, high is defined as 50% of signal value and low is defined as

50% of signal value.

NOTE

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 33 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

Table 33. SDRAM Refresh Timing Parameters

ID Parameter Symbol Min Max Unit

SD1 SDRAM clock high-level width tCH 3.4 4.1 ns

SD2 SDRAM clock low-level width

tCL 3.4 4.1 ns

SD3 SDRAM clock cycle time tCK 7.5 — ns

SD6 Address setup time tAS 1.8 — ns

SD7 Address hold time tAH 1.8 — ns

SD10 Precharge cycle period

SD10 and SD11 are determined by SDRAM controller register settings.

tRP 1 4 clock

SD11 Auto precharge command period

tRC 2 20 clock