Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3

44 Freescale Semiconductor

Electrical Characteristics

NOTE

SDR SDRAM CLK parameters are being measured from the 50%

point—that is, high is defined as 50% of signal value and low is defined as

50% of signal value.

NOTE

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 32 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

Figure 35. SDRAM Refresh Timing Diagram

SD13 Data setup time tDS 2.0 — ns

SD14 Data hold time tDH 1.3 — ns

SD11 and SD12 are determined by SDRAM controller register settings.

Table 32. SDR SDRAM Write Timing Parameters (continued)

ID Parameter Symbol Min Max Unit

CAS

RAS

ADDR

ROW/BA

SD6

SD7

SD11

SD10

SDCLK

SD1

SD2

SDCLK

SD3