Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 43
Figure 34. SDR SDRAM Write Cycle Timing Diagram
Table 32. SDR SDRAM Write Timing Parameters
ID Parameter Symbol Min Max Unit
SD1 SDRAM clock high-level width tCH 3.4 4.1 ns
SD2 SDRAM clock low-level width
tCL 3.4 4.1 ns
SD3 SDRAM clock cycle time tCK 7.5 — ns
SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.0 — ns
SD5 CS, RAS, CAS, WE, DQM, CKE hold time tCMH 1.8 — ns
SD6 Address setup time tAS 2.0 — ns
SD7 Address hold time tAH 1.8 — ns
SD11 Precharge cycle period
1
tRP 1 4 clock
SD12 Active to read/write command delay
1
tRCD 1 8 clock
CS
CAS
WE
RAS
ADDR
DQ
DQM
BA
ROW / BA
COL/BA
DATA
SD4
SD4
SD4SD4
SD5
SD5
SD5
SD5
SD7
SD6
SD12
SD13
SD14
SD11
SDCLK
SD1
SD3
SD2
SDCLK