Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
42 Freescale Semiconductor
Electrical Characteristics
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
NOTE
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 31 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
SD9 Data out hold time
1
tOH 1.8 — ns
SD10 Active to read/write command period tRC 10 — clock
1
Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see
Ta bl e 3 5 and Ta bl e 3 6 .
Table 31. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
ID Parameter Symbol Min Max Unit