Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 41
Figure 33. SDRAM Read Cycle Timing Diagram
Table 31. DDR/SDR SDRAM Read Cycle Timing Parameters
ID Parameter Symbol Min Max Unit
SD1 SDRAM clock high-level width tCH 3.4 4.1 ns
SD2 SDRAM clock low-level width
tCL 3.4 4.1 ns
SD3 SDRAM clock cycle time tCK 7.5 — ns
SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.0 — ns
SD5 CS, RAS, CAS, WE, DQM, CKE hold time tCMH 1.8 — ns
SD6 Address setup time tAS 2.0 — ns
SD7 Address hold time tAH 1.8 — ns
SD8 SDRAM access time tAC — 6.47 ns
SDCLK
WE
ADDR
DQ
DQM
COL/BA
Data
CS
CAS
RAS
Note: CKE is high during the read/write cycle.
SD4
SD1
SD3
SD2
SD4
SD4
SD4
SD4
SD5
SD5
SD5
SD5
SD5
SD6
SD7
SD10
SD8
SD9
SDCLK
ROW/BA