Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
40 Freescale Semiconductor
Electrical Characteristics
Figure 31. Muxed A/D Mode Timing Diagram for Asynchronous Write Access—
WSC=7, LBA=1, LBN=1, LAH=1
Figure 32. Muxed A/D Mode Timing Diagram for Asynchronous Read Access—
WSC=7, LBA=1, LBN=1, LAH=1, OEA=7
4.3.9.3 ESDCTL Electrical Specifications
Figure 33, Figure 34, Figure 35, Figure 36, Figure 37, and Figure 38 depict the timings pertaining to the
ESDCTL module, which interfaces Mobile DDR or SDR SDRAM. Table 31, Table 32, Table 33, Table 34,
Table 35, and Table 36 list the timing parameters.
Write
BCLK
ADDR/
RW
LBA
OE
EB[y]
CS
[x]
Address V1
Write Data
Last Valid Addr
M_DATA
WE1
WE2
WE3
WE4
WE6
WE5
WE9
WE10
WE11
WE12
WE13
WE14
BCLK
ADDR/
RW
LBA
OE
EB[y]
CS
[x]
Address V1
Read Data
Last Valid Addr
M_DATA
WE2
WE3
WE4
WE11
WE12
WE7
WE8
WE9
WE10
WE15
WE16
WE1