Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
4 Freescale Semiconductor
Functional Description and Application Information
1.3 Block Diagram
Figure 1 shows the MCIMX31C simplified interface block diagram.
Figure 1. MCIMX31C Simplified Interface Block Diagram
2 Functional Description and Application Information
2.1 ARM11 Microprocessor Core
The CPU of the MCIMX31C is the ARM1136JF-S core based on the ARM v6 architecture. It supports the
ARM Thumb
®
instruction sets, features Jazelle
®
technology (which enables direct execution of Java byte
codes), and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.
The ARM1136JF-S processor core features:
• Integer unit with integral EmbeddedICE
™
logic
• Eight-stage pipeline
• Branch prediction with return stack
• Low-interrupt latency
External Memory
AP Peripherals
SRAM, PSRAM,
SDRAM
NAND Flash,
SmartMedia
GPU *
Camera
MPEG-4
Baseband
SD
Card
Fast
IrDA
USB
Image Processing Unit (IPU)
Parallel
Sensor (2)
Serial
LCD
Timers
AUDMUX
SSI (2)
UART (5)
GPT
PWM
EPIT (2)
RTC
GPIO
WDOG
1-WIRE ®
CSPI (3)
I
2
C (3)
FIR
KPP
CCM
ARM11
TM
Platform
I-Cache
D-Cache
L2-Cache
ROMPATCH
VFP
SDMA
USB-OTG
IIM
Expansion
SIM
ATA
PCMCIA/CF
Mem Stick (2)
SDHC (2)
USB Host (2)
* GPU unavailable for i.MX31L
Inversion and Rotation
Camera Interface
Blending
Display/TV Ctl
Pre & Post Processing
Display (2)
NOR Flash
DDR
WLAN
Bluetooth
Interface (EMI)
Power
Management
IC
PC
Card
PC
Card
Host/Device
Mouse
Keyboard
Ta mp e r
Detection
Serial
EPROM
Video Encoder
8 x 8
Keypad
GPS
ATA
Hard Drive
ARM1136JF-S
TM
MAX
Memory
Internal
Security
RNGA
SCC
RTIC
Debug
ECT
SJC
ETM