Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 39
Figure 29. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses—
WSC=2, SYNC=1, DOL=0
Figure 30. Synchronous Memory TIming Diagram for Burst Write Access—
BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1
Last Valid Addr
Address V1 Address V2
V1
V1+2
V2
V2+2
BCLK
ADDR
ECB
DATA
Halfword
Halfword
CS[x]
RW
LBA
OE
EB[y]
Halfword Halfword
WE1
WE2
WE4
WE7
WE8
WE9
WE10
WE11
WE12
WE15
WE15
WE16
WE16
WE17 WE17
WE18
WE18
WE3
Last Valid Addr
BCLK
ADDR
DATA
CS[x]
RW
LBA
OE
EB[y]
ECB
Address V1
V1
V1+4 V1+12V1+8
WE9
WE1
WE2
WE3 WE4
WE5
WE6
WE10
WE11
WE13
WE13
WE14
WE14
WE17
WE18
WE12