Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
38 Freescale Semiconductor
Electrical Characteristics
Figure 27. Asynchronous Memory Timing Diagram for Read Access—WSC=1
Figure 28. Asynchronous Memory Timing Diagram for Write Access—
WSC=1, EBWA=1, EBWN=1, LBN=1
Last Valid Address
V1
V1
BCLK
ADDR
DATA
RW
LBA
OE
EB[y]
CS
[x]
Next Address
WE1
WE2
WE3
WE4
WE7
WE8
WE10
WE9
WE11
WE12
WE15
WE16
Last Valid Address
V1
V1
BCLK
ADDR
DATA
RW
LBA
OE
EB[y]
CS
[x]
Next Address
WE1
WE2
WE3
WE4
WE5
WE6
WE9
WE10
WE11
WE12
WE13
WE14