Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 37
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Test conditions: load capacitance, 25 pF. Recommended drive strength for all
controls, address, and BCLK is Max drive.
Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, and Figure 32 depict some examples of
basic WEIM accesses to external memory devices with the timing parameters mentioned in
Table 30 for specific control parameter settings.
WE8 Clock rise/fall to OE Invalid –3 3 ns
WE9 Clock rise/fall to EB
[x] Valid –3 3 ns
WE10 Clock rise/fall to EB
[x] Invalid –3 3 ns
WE11 Clock rise/fall to LBA
Valid –3 3 ns
WE12 Clock rise/fall to LBA
Invalid –3 3 ns
WE13 Clock rise/fall to Output Data Valid –2.5 4 ns
WE14 Clock rise to Output Data Invalid –2.5 4 ns
WE15 Input Data Valid to Clock rise, FCE=0
FCE=1
8
2.5
—
ns
WE16 Clock rise to Input Data Invalid, FCE=0
FCE=1
–2
–2
—
ns
WE17 ECB
setup time, FCE=0
FCE=1
6.5
3.5
—
ns
WE18 ECB
hold time, FCE=0
FCE=1
–2
2
—
ns
WE19 DTACK
setup time
1
0—ns
WE20 DTACK
hold time
1
4.5 — ns
WE21 BCLK High Level Width
2, 3
—T/2–3ns
WE22 BCLK Low Level Width
2, 3
—T/2–3ns
WE23 BCLK Cycle time
2
15 — ns
1
Applies to rising edge timing
2
BCLK parameters are being measured from the 50% VDD.
3
The actual cycle time is derived from the AHB bus clock frequency.
Table 30. WEIM Bus Timing Parameters (continued)
ID Parameter Min Max Unit