Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
34 Freescale Semiconductor
Electrical Characteristics
Figure 25. Read Data Latch Cycle Timing DIagram
Table 29. NFC Timing Parameters
1
1
The flash clock maximum frequency is 50 MHz.
ID Parameter Symbol
Timing
T = NFC Clock Cycle
2
2
Subject to DPLL jitter specification on Table 28, "DPLL Specifications," on page 31.
Example Timing for
NFC Clock
≈ 33 MHz
T = 30 ns
Unit
Min Max Min Max
NF1 NFCLE Setup Time tCLS T–1.0 ns — 29 — ns
NF2 NFCLE Hold Time tCLH T–2.0 ns — 28 — ns
NF3 NFCE
Setup Time tCS T–1.0 ns — 29 — ns
NF4 NFCE
Hold Time tCH T–2.0 ns — 28 — ns
NF5 NF_WP
Pulse Width tWP T–1.5 ns 28.5 ns
NF6 NFALE Setup Time tALS T — 30 — ns
NF7 NFALE Hold Time tALH T–3.0 ns — 27 — ns
NF8 Data Setup Time tDS T — 30 — ns
NF9 Data Hold Time tDH T–5.0 ns — 25 — ns
NF10 Write Cycle Time tWC 2T 60 ns
NF11 NFWE
Hold Time tWH T–2.5 ns 27.5 ns
NF12 Ready to NFRE
Low tRR 6T — 180 — ns
NF13 NFRE
Pulse Width tRP 1.5T — 45 — ns
NF14 READ Cycle Time tRC 2T — 60 — ns
NF15 NFRE
High Hold Time tREH 0.5T–2.5 ns 12.5 — ns
NF16 Data Setup on READ tDSR N/A 10 — ns
NF17 Data Hold on READ tDHR N/A 0 — ns
NFCLE
NFCE
NFRE
NFRB
NFIO[15:0]
Data from NF
NF13
NF15
NF14
NF17
NF12
NF16