Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
32 Freescale Semiconductor
Electrical Characteristics
4.3.9 EMI Electrical Specifications
This section provides electrical parametrics and timings for EMI module.
4.3.9.1 NAND Flash Controller Interface (NFC)
The NFC supports normal timing mode, using two flash clock cycles for one access of RE and WE. AC
timings are provided as multiplications of the clock cycle and fixed delay. Figure 22, Figure 23, Figure 24,
and Figure 25 depict the relative timing requirements among different signals of the NFC at module level,
for normal mode, and Table 29 lists the timing parameters.
Figure 22. Command Latch Cycle Timing DIagram
Phase lock time — — 100 µs In addition to the frequency
Maximum allowed PLL supply voltage ripple — — 25 mV F
modulation
< 50 kHz
Maximum allowed PLL supply voltage ripple — — 20 mV 50 kHz < F
modulation
< 300 kHz
Maximum allowed PLL supply voltage ripple — — 25 mV F
modulation
> 300 kHz
PLL output clock phase jitter — — 5.2 ns Measured on CLKO pin
PLL output clock period jitter — — 420 ps Measured on CLKO pin
1
The user or board designer must take into account that the use of a frequency other than 26 MHz would require adjustment to
the DPTC–DVFS table, which is incorporated into operating system code.
2
The PLL reference frequency must be ≤ 35 MHz. Therefore, for frequencies between 35 MHz and 70 MHz, program the
predivider to divide by 2 or more. If the CKIH frequency is above 70 MHz, program the predivider to 3 or more. For PD bit
description, see the reference manual.
Table 28. DPLL Specifications (continued)
Parameter Min Typ Max Unit Comments
NFCLE
NFCE
NFWE
NFALE
NFIO[7:0]
Command
NF9
NF8
NF1
NF2
NF5
NF3
NF4
NF6 NF7