Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 31
4.3.8 DPLL Electrical Specifications
The three PLL’s of the MCIMX31C (MCU, USB, and Serial PLL) are all based on same DPLL design.
The characteristics provided herein apply to all of them, except where noted explicitly. The PLL
characteristics are provided based on measurements done for both sources—external clock source (CKIH),
and FPM (Frequency Pre-Multiplier) source.
4.3.8.1 Electrical Specifications
Table 28 lists the DPLL specification.
Table 27. CSPI Interface Timing Parameters
ID Parameter Symbol Min Max Units
CS1 SCLK Cycle Time t
clk
60 — ns
CS2 SCLK High or Low Time t
SW
30 — ns
CS3 SCLK Rise or Fall t
RISE/FALL
—7.6ns
CS4 SSx pulse width t
CSLH
25 — ns
CS5 SSx Lead Time (CS setup time) t
SCS
25 — ns
CS6 SSx Lag Time (CS hold time) t
HCS
25 — ns
CS7 Data Out Setup Time t
Smosi
5—ns
CS8 Data Out Hold Time t
Hmosi
5—ns
CS9 Data In Setup Time t
Smiso
6—ns
CS10 Data In Hold Time t
Hmiso
5—ns
CS11 S
PI_RDY Setup Time
1
1
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
t
SRDY
——ns
Table 28. DPLL Specifications
Parameter Min Typ Max Unit Comments
CKIH frequency 15 26
1
75
2
MHz —
CKIL frequency
(Frequency Pre-multiplier (FPM) enable mode)
— 32; 32.768, 38.4 — kHz FPM lock time ≈ 480 µs.
Predivision factor (PD bits) 1 — 16 — —
PLL reference frequency range after Predivider 15 — 35 MHz 15 ≤ CKIH frequency/PD ≤ 35 MHz
15 ≤ FPM output/PD ≤ 35 MHz
PLL output frequency range:
MPLL and SPLL
UPLL
52
190
—
400
240
MHz —
Maximum allowed reference clock phase noise. — —
± 100 ps —
Frequency lock time
(FOL mode or non-integer MF)
— — 398 — Cycles of divided reference clock.