Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 21
Figure 8 depicts Write 1 Sequence timing, Figure 9 depicts the Read Sequence timing, and Table 20 lists
the timing parameters.
Figure 8. Write 1 Sequence Timing Diagram
Figure 9. Read Sequence Timing Diagram
4.3.5 ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses ATA parameters. For a detailed description, refer to the ATA specification.
The user needs to use level shifters for 3.3 Volt or 5.0 Volt compatibility on the ATA interface.
The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast
UDMA mode operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.
Table 19. WR0 Sequence Timing Parameters
ID Parameter Symbol Min Typ Max Units
OW5 Write 0 Low Time t
WR0_low
60 100 120 µs
OW6 Transmission Time Slot t
SLOT
OW5 117 120 µs
Table 20. WR1/RD Timing Parameters
ID Parameter Symbol Min Typ Max Units
OW7 Write 1 / Read Low Time t
LOW1
1515µs
OW8 Transmission Time Slot t
SLOT
60 117 120 µs
OW9 Release Time t
RELEASE
15 — 45 µs
OW7
OW8
1-Wire bus
(BATT_LINE)
OW7
OW8
OW9
1-Wire bus
(BATT_LINE)