Technical data

MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
16 Freescale Semiconductor
Electrical Characteristics
Figure 3. Option 2 Power-Up Sequence (Silicon Revision 2.0 and 2.0.1)
4.2.2 Powering Down
The power-down sequence should be completed as follows:
1. Lower the FUSE_VDD supply (when in write mode).
2. Lower the remaining supplies.
4.3 Module-Level Electrical Specifications
This section contains the MCIMX31C electrical information including timing specifications, arranged in
alphabetical order by module name.
4.3.1 I/O Pad (PADIO) Electrical Specifications
This section specifies the AC/DC characterization of functional I/O of the MCIMX31C. There are two
main types of I/O: regular and DDR. In this document, the “Regular” type is referred to as GPIO.
4.3.1.1 DC Electrical Characteristics
The MCIMX31C I/O parameters appear in Table 12 for GPIO. See Table 7, "Operating Ranges," on page
12 for temperature and supply voltage ranges.
Release POR
QVCC, QVCC1, QVCC4
IOQVDD, NVCC1, NVCC3–10, NVCC2, NVCC21, NVCC22
Hold POR Asserted
1
1, 2,3
Notes:
1
The board design must guarantee that supplies reach
90% level before transition to the next state, using Power
Management IC or other means.
2
The NVCC1 supply must not precede IOQVDD by more
than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD
is powered up first, there are no restrictions.
3
Raising NVCC2, NVCC21, and NVCC22 at the same
time as IOQVDD does not produce the slight increase in
current drain on IOQVDD (as described in Figure 2,
Note 5).
4
FUSE_VDD should not be driven on power-up for Silicon
Revision2.0 and 2.0.1. This supply is dedicated for fuse
burning (programming), and should not be driven upon
boot-up.
FVCC, MVCC, SVCC, UVCC
1
4