Technical data

Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor 15
4.2 Supply Power-Up/Power-Down Requirements and Restrictions
Any MCIMX31C board design must comply with the power-up and power-down sequence guidelines as
described in this section to guarantee reliable operation of the device. Any deviation from these sequences
may result in any or all of the following situations:
• Cause excessive current during power-up phase
• Prevent the device from booting
• Cause irreversible damage to the MCIMX31C (worst-case scenario)
4.2.1 Powering Up
The Power On Reset (POR) pin must be kept asserted (low) throughout the power-up sequence. Power-up
logic must guarantee that all power sources reach their target values prior to the release (de-assertion) of
POR. Figure 2 and Figure 3 show two options of the power-up sequence.
NOTE
Stages need to be performed in the order shown; however, within each stage,
supplies can be powered up in any order. For example, supplies IOQVDD, NVCC1,
and NVCC3 through NVCC10 do not need to be powered up in the order shown.
CAUTION
NVCC6 and NVCC9 must be at the same voltage potential. These supplies
are connected together on-chip to optimize ESD damage immunity.
Figure 2. Option 1 Power-Up Sequence for Silicon Revision 2.0 and 2.0.1
Release POR
QVCC, QVCC1, QVCC4
IOQVDD, NVCC1, NVCC3–10
NVCC2, NVCC21, NVCC22
Hold POR Asserted
1
1, 2
1, 3
Notes:
1
The board design must guarantee that supplies reach 90% level before
transition to the next state, using Power Management IC or other
means.
2
The NVCC1 supply must not precede IOQVDD by more than 0.2 V until
IOQVDD has reached 1.5 V. If IOQVDD is powered up first, there are
no restrictions.
3
The parallel paths in the flow indicate that supply group NVCC2,
NVCC21, and NVCC22, and supply group FVCC, MVCC, SVCC, and
UVCC ramp-ups are independent.
4
FUSE_VDD should not be driven on power-up for Silicon Revision 2.0
and 2.0.1. This supply is dedicated for fuse burning (programming),
and should not be driven upon boot-up.
5
Raising IOQVDD before NVCC21 produces a slight increase in current
drain on IOQVDD of approximately 3–5 mA. The current increase will
not damage the IC. Refer to Errata ID TLSbo91750 for details.
FVCC, MVCC, SVCC, UVCC
1,3
4