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Freescale Semiconductor

Data Sheet: Technical Data

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Document Number: MCIMX31C

Rev. 4.3, 2/2010

MCIMX31C and

MCIMX31LC

Package Information

Plastic Package

Case 1931 19 x 19 mm, 0.8 mm Pitch

Ordering Information

See Table 1 on page 3 for ordering information.

1 Introduction

The MCIMX31C and MCIMX31LC multimedia

applications processors represent the next step in

low-power, high-performance application processors.

Unless otherwise specified, the material in this data sheet

is applicable to both the MCIMX31C and MCIMX31LC

processors and referred to singularly throughout this

document as MCIMX31C. The MCIMX31LC does not

include a graphics processing unit (GPU).

Based on an ARM11™ microprocessor core, the

MCIMX31C provides the performance with low power

consumption required by modern digital devices such

as:

• Automotive infotainment and navigation

• Industrial control (human interface)

The MCIMX31C takes advantage of the

ARM1136JF-S™ core running at 400 MHz, and is

optimized for minimal power consumption using the

most advanced techniques for power saving (DVFS,

power gating, clock gating). With 90 nm technology and

dual-Vt transistors (two threshold voltages), the

MCIMX31C and

MCIMX31LC

Multimedia Applications

Processors for Industrial and

Automotive Products

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Ordering Information . . . . . . . . . . . . . . . . . . . . . .3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Functional Description and Application Information 4

ARM11 Microprocessor Core . . . . . . . . . . . . . . . .4

Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . .6

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .9

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .9

Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . .9

Supply Power-Up/Power-Down Requirements and

Restrictions . . . . . . . . . . . . . . . . . . . . . . . .15

Module-Level Electrical Specifications . . . . . . . .16

Package Information and Pinout . . . . . . . . . . . . . .99

MAPBGA Production Package 473 19 x 19 mm,

0.8 mm Pitch . . . . . . . . . . . . . . . . . . . . . .100

Product Documentation . . . . . . . . . . . . . . . . . . . .106

Revision History . . . . . . . . . . . . . . . . . . . . . . . .107

Summary of content (108 pages)

PAGE 1
Freescale Semiconductor Data Sheet: Technical Data Document Number: MCIMX31C Rev. 4.3, 2/2010 MCIMX31C and MCIMX31LC MCIMX31C and MCIMX31LC Multimedia Applications Processors for Industrial and Automotive Products 1 Introduction The MCIMX31C and MCIMX31LC multimedia applications processors represent the next step in low-power, high-performance application processors.
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Introduction MCIMX31C provides the optimal performance versus leakage current balance. The performance of the MCIMX31C is boosted by a multi-level cache system, and features peripheral devices such as an MPEG-4 Hardware Encoder (VGA, 30 fps), an Autonomous Image Processing Unit, a Vector Floating Point (VFP11) co-processor, and a RISC-based SDMA controller. The MCIMX31C supports connections to various types of external memories, such as DDR, NAND Flash, NOR Flash, SDRAM, and SRAM.
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Introduction 1.2 Ordering Information Table 1 provides the ordering information for the MCIMX31C. Table 1. MCIMX31C and MCIMX31LC Ordering Information1 Silicon Revision Operating Temperature Range (°C) MCIMX31CVMN4C! 2.0 –40 to 85 MCIMX31LCVMN4C! 2.0 –40 to 85 MCIMX31CVMN4D! 2.0.1 –40 to 85 MCIMX31LCVMN4D! 2.0.1 –40 to 85 MCIMX31CJMN4C 2.0.1 –40 to 85 MCIMX31LCJMN4D 2.0.1 –40 to 85 MCIMX31CJMN4D 2.0.1 –40 to 85 Part Number Package2 19 x 19 mm, 0.
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Functional Description and Application Information 1.3 Block Diagram Figure 1 shows the MCIMX31C simplified interface block diagram.
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Functional Description and Application Information • • • • • • • • Instruction and data memory management units (MMUs), managed using micro TLB structures backed by a unified main TLB Instruction and data L1 caches, including a non-blocking data cache with Hit-Under-Miss Virtually indexed/physically addressed L1 caches 64-bit interface to both L1 caches Write buffer (bypassable) High-speed Advanced Micro Bus Architecture (AMBA)™ L2 interface Vector Floating Point co-processor (VFP) for 3D graphics and oth
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Functional Description and Application Information 2.2 Module Inventory Table 3 shows an alphabetical listing of the modules in the multimedia applications processor. For extended descriptions of the modules, see the reference manual. A cross-reference is provided to the electrical specifications and timing information for each module with external signal connections. Table 3.
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Functional Description and Application Information Table 3. Digital and Analog Modules (continued) Block Mnemonic Fusebox Block Name Functional Grouping Brief Description Section/ Page Fusebox ROM The Fusebox is a ROM that is factory configured by Freescale. GPIO General Purpose I/O Module Pins The GPIO provides several groups of 32-bit bidirectional, general purpose I/O. This peripheral provides dedicated general-purpose signals that can be configured as either inputs or outputs.
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Functional Description and Application Information Table 3. Digital and Analog Modules (continued) Block Mnemonic Block Name Functional Grouping Section/ Page Brief Description Security Controller Module Security SDHC Secured Digital Host Controller Connectivity The SDHC controls the MMC (MultiMediaCard), SD (Secure Digital) Peripheral memory, and I/O cards by sending commands to cards and performing data accesses to and from the cards.
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Signal Descriptions 3 Signal Descriptions Signal descriptions are in the reference manual. Special signal considerations are listed following this paragraph. The BGA ball assignment is in Section 5, “Package Information and Pinout,” on page 99. Special Signal Considerations: • Tamper detect (GPIO1_6) Tamper detect logic is used to issue a security violation. This logic is activated if the tamper detect input is asserted. The tamper detect logic is disabled after reset.
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Electrical Characteristics Table 4. MCIMX31C Chip-Level Conditions For these characteristics, … Topic appears … Table 5, “Absolute Maximum Ratings” on page 10 Table 6, “Thermal Resistance Data—19 × 19 mm Package” on page 10 Table 7, “Operating Ranges” on page 12 Table 8, “Specific Operating Ranges for Silicon Revision 2.0 and 2.0.1” on page 12 Table 9, “Interface Frequency” on page 13 Section 4.1.1, “Supply Current Specifications” on page 14 Section 4.
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Electrical Characteristics Table 6. Thermal Resistance Data—19 Rating × 19 mm Package (continued) Board Symbol Value Unit Notes Four layer board (2s2p) RθJMA 25 °C/W 1, 2, 3 Junction to Board — RθJB 19 °C/W 1, 3 Junction to Case (Top) — RθJCtop 10 °C/W 1, 4 Junction to Package Top (natural convection) — ΨJT 2 °C/W 1, 5 Junction to Ambient (@200 ft/min) 1. 2. 3. 4. 5.
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Electrical Characteristics Table 7 provides the operating ranges. NOTE The term NVCC in this section refers to the associated supply rail of an input or output. The association is shown in the Signal Multiplexing chapter of the reference manual. CAUTION NVCC6 and NVCC9 must be at the same voltage potential. These supplies are connected together on-chip to optimize ESD damage immunity. Table 7.
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Electrical Characteristics 1 2 In read mode, FUSE_VDD should be floated or grounded. Fuses might be inadvertently blown if written to while the voltage is below the minimum. Table 9 provides information for interface frequency limits. For more details about clocks characteristics, see Section 4.3.8, “DPLL Electrical Specifications” on page 31 and Section 4.3.3, “Clock Amplifier Module (CAMP) Electrical Characteristics” on page 19. Table 9.
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Electrical Characteristics 4.1.1 Supply Current Specifications Table 11 shows the core current consumption for –40°C to 85°C for Silicon Revision 2.0 and 2.0.1 for the MCIMX31C. Table 11. Current Consumption for –40°C to 85°C1, 2 for Silicon Revision 2.0 and 2.0.1 Mode Conditions QVCC (Peripheral) QVCC1 (ARM) FVCC + MVCC + SVCC + UVCC Unit (PLL) QVCC4 (L2) Typ Max Typ Max Typ Max Typ Max • QVCC = 0.95 V • ARM and L2 caches are power gated (QVCC1 = QVCC4 = 0 V) • All PLLs are off, VCC = 1.
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Electrical Characteristics 4.2 Supply Power-Up/Power-Down Requirements and Restrictions Any MCIMX31C board design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the device. Any deviation from these sequences may result in any or all of the following situations: • Cause excessive current during power-up phase • Prevent the device from booting • Cause irreversible damage to the MCIMX31C (worst-case scenario) 4.2.
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Electrical Characteristics Notes: 1 Hold POR Asserted 2 QVCC, QVCC1, QVCC4 1 3 1, 2,3 IOQVDD, NVCC1, NVCC3–10, NVCC2, NVCC21, NVCC22 4 The board design must guarantee that supplies reach 90% level before transition to the next state, using Power Management IC or other means. The NVCC1 supply must not precede IOQVDD by more than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD is powered up first, there are no restrictions.
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Electrical Characteristics NOTE The term NVCC in this section refers to the associated supply rail of an input or output. The association is shown in the Signal Multiplexing chapter of the reference manual. NVCC for Table 12 refers to NVCC1 and NVCC3–10; QVCC refers to QVCC, QVCC1, and QVCC4. Table 12. GPIO DC Electrical Parameters Parameter High-level output voltage Low-level output voltage Symbol Test Conditions Min Typ Max Units VOH IOH = –1 mA NVCC –0.15 — — V IOH = specified Drive 0.
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Electrical Characteristics The MCIMX31C I/O parameters appear in Table 13 for DDR (Double Data Rate). See Table 7, "Operating Ranges," on page 12 for temperature and supply voltage ranges. NOTE NVCC for Table 13 refers to NVCC2, NVCC21, and NVCC22. Table 13. DDR (Double Data Rate) I/O DC Electrical Parameters Parameter High-level output voltage Low-level output voltage Symbol Test Conditions Min Typ Max Units VOH IOH = –1 mA NVCC –0.12 — — V IOH = specified Drive 0.
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Electrical Characteristics Table 14. AC Electrical Characteristics of Slow1 General I/O ID PA1 1 Parameter Symbol Test Condition Min Typ Max Units Output Transition Times (Max Drive) tpr 25 pF 50 pF 0.92 1.5 1.95 2.98 3.17 4.75 ns Output Transition Times (High Drive) tpr 25 pF 50 pF 1.52 2.75 — 4.81 8.42 ns Output Transition Times (Std Drive) tpr 25 pF 50 pF 2.79 5.39 — 8.56 16.43 ns Fast/slow characteristic is selected per GPIO (where available) by “slew rate” control.
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Electrical Characteristics Table 17. Clock Amplifier Electrical Characteristics for CKIH Input Parameter Min Typ Max Units Input Frequency 15 — 75 MHz VIL (for square wave input) 0 — 0.3 V VIH (for square wave input) (VDD 1– 0.25) — 3 V Sinusoidal Input Amplitude 0.4 2 — VDD Vp-p 45 50 55 % Duty Cycle 1 2 VDD is the supply voltage of CAMP. See reference manual. This value of the sinusoidal input will be measured through characterization. 4.3.
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Electrical Characteristics Table 19. WR0 Sequence Timing Parameters ID Parameter OW5 Write 0 Low Time OW6 Transmission Time Slot Symbol Min Typ Max Units tWR0_low 60 100 120 µs tSLOT OW5 117 120 µs Figure 8 depicts Write 1 Sequence timing, Figure 9 depicts the Read Sequence timing, and Table 20 lists the timing parameters. OW8 1-Wire bus (BATT_LINE) OW7 Figure 8. Write 1 Sequence Timing Diagram OW8 1-Wire bus (BATT_LINE) OW7 OW9 Figure 9. Read Sequence Timing Diagram Table 20.
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Electrical Characteristics When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided. 4.3.5.
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Electrical Characteristics Table 21. ATA Timing Parameters (continued) 1 Value/ Contributing Factor1 Name Description tskew5 Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) cable tskew6 Max difference in cable propagation delay without accounting for ground bounce cable Values provided where applicable. 4.3.5.
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Electrical Characteristics Figure 11. Multiword DMA (MDMA) Timing Table 23. PIO Write Timing Parameters ATA Parameter Parameter from Figure 11 Controlling Variable Value t1 t1 t1 (min) = time_1 * T – (tskew1 + tskew2 + tskew5) time_1 t2 t2w t9 t9 t9 (min) = time_9 * T – (tskew1 + tskew2 + tskew6) t3 — t3 (min) = (time_2w – time_on)* T – (tskew1 + tskew2 +tskew5) t4 t4 t4 (min) = time_4 * T – tskew1 time_4 tA tA tA = (1.
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Electrical Characteristics Figure 12. MDMA Read Timing Diagram Figure 13. MDMA Write Timing Diagram Table 24. MDMA Read and Write Timing Parameters ATA Parameter Parameter from Figure 12, Figure 13 tm, ti tm tm (min) = ti (min) = time_m * T – (tskew1 + tskew2 + tskew5) time_m td td, td1 td1.(min) = td (min) = time_d * T – (tskew1 + tskew2 + tskew6) time_d tk tk tk.
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Electrical Characteristics 4.3.5.3 UDMA In Timing Figure 14 shows timing when the UDMA in transfer starts, Figure 15 shows timing when the UDMA in host terminates transfer, Figure 16 shows timing when the UDMA in device terminates transfer, and Table 25 lists the timing parameters for UDMA in burst. Figure 14. UDMA In Transfer Starts Timing Diagram Figure 15. UDMA In Host Terminates Transfer Timing Diagram MCIMX31C/MCIMX31LC Technical Data, Rev. 4.
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Electrical Characteristics Figure 16. UDMA In Device Terminates Transfer Timing Diagram Table 25.
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Electrical Characteristics 4.3.5.4 UDMA Out Timing Figure 17 shows timing when the UDMA out transfer starts, Figure 18 shows timing when the UDMA out host terminates transfer, Figure 19 shows timing when the UDMA out device terminates transfer, and Table 26 lists the timing parameters for UDMA out burst. Figure 17. UDMA Out Transfer Starts Timing Diagram Figure 18. UDMA Out Host Terminates Transfer Timing Diagram MCIMX31C/MCIMX31LC Technical Data, Rev. 4.
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Electrical Characteristics Figure 19. UDMA Out Device Terminates Transfer Timing Diagram Table 26.
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Electrical Characteristics 4.3.6 AUDMUX Electrical Specifications The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is hence governed by the SSI module. Please refer to their respective electrical specifications. 4.3.7 CSPI Electrical Specifications This section describes the electrical information of the CSPI. 4.3.7.
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Electrical Characteristics Table 27. CSPI Interface Timing Parameters ID 1 Parameter Symbol Min Max Units CS1 SCLK Cycle Time tclk 60 — ns CS2 SCLK High or Low Time tSW 30 — ns CS3 SCLK Rise or Fall tRISE/FALL — 7.
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Electrical Characteristics Table 28. DPLL Specifications (continued) Parameter Min Typ Max Unit Comments Phase lock time — — 100 µs Maximum allowed PLL supply voltage ripple — — 25 mV Fmodulation < 50 kHz Maximum allowed PLL supply voltage ripple — — 20 mV 50 kHz < Fmodulation < 300 kHz Maximum allowed PLL supply voltage ripple — — 25 mV Fmodulation > 300 kHz PLL output clock phase jitter — — 5.
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Electrical Characteristics NFCLE NF1 NF4 NF3 NFCE NF10 NF11 NF5 NFWE NF7 NF6 NFALE NF8 NF9 Address NFIO[7:0] Figure 23. Address Latch Cycle Timing DIagram NFCLE NF1 NF3 NFCE NF10 NF11 NF5 NFWE NF7 NF6 NFALE NF8 NF9 NFIO[15:0] Data to NF Figure 24. Write Data Latch Cycle Timing DIagram MCIMX31C/MCIMX31LC Technical Data, Rev. 4.
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Electrical Characteristics NFCLE NFCE NF14 NF15 NF13 NFRE NF17 NF16 NFRB NF12 NFIO[15:0] Data from NF Figure 25. Read Data Latch Cycle Timing DIagram Table 29. NFC Timing Parameters1 ID 1 2 Parameter Symbol Timing T = NFC Clock Cycle2 Example Timing for NFC Clock ≈ 33 MHz T = 30 ns Min Max Min Max Unit NF1 NFCLE Setup Time tCLS T–1.0 ns — 29 — ns NF2 NFCLE Hold Time tCLH T–2.0 ns — 28 — ns NF3 NFCE Setup Time tCS T–1.0 ns — 29 — ns NF4 NFCE Hold Time tCH T–2.
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Electrical Characteristics NOTE High is defined as 80% of signal value and low is defined as 20% of signal value. NOTE Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is approximately 33 MHz (30 ns). All timings are listed according to this NFC clock frequency (multiples of NFC clock phases), except NF16 and NF17, which are not NFC clock related. 4.3.9.
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Electrical Characteristics WEIM Outputs Timing WE22 WE21 ... BCLK WE23 WE1 WE2 WE3 WE4 WE5 WE6 WE7 WE8 WE9 WE10 WE11 WE12 WE13 WE14 Address CS[x] RW OE EB[x] LBA Output Data WEIM Inputs Timing BCLK WE16 Input Data WE15 WE18 ECB WE17 WE20 DTACK WE19 Figure 26. WEIM Bus Timing Diagram Table 30. WEIM Bus Timing Parameters ID Parameter Min Max Unit WE1 Clock fall to Address Valid –0.5 2.5 ns WE2 Clock rise/fall to Address Invalid –0.
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Electrical Characteristics Table 30. WEIM Bus Timing Parameters (continued) ID Parameter Min Max Unit WE8 Clock rise/fall to OE Invalid –3 3 ns WE9 Clock rise/fall to EB[x] Valid –3 3 ns WE10 Clock rise/fall to EB[x] Invalid –3 3 ns WE11 Clock rise/fall to LBA Valid –3 3 ns WE12 Clock rise/fall to LBA Invalid –3 3 ns WE13 Clock rise/fall to Output Data Valid –2.5 4 ns WE14 Clock rise to Output Data Invalid –2.
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Electrical Characteristics BCLK WE2 WE1 V1 Last Valid Address ADDR Next Address WE3 WE4 WE11 WE12 WE7 WE8 WE9 WE10 CS[x] RW LBA OE EB[y] WE16 V1 DATA WE15 Figure 27. Asynchronous Memory Timing Diagram for Read Access—WSC=1 BCLK WE2 WE1 ADDR CS[x] Last Valid Address WE3 WE4 WE5 WE6 RW LBA Next Address V1 WE11 WE12 OE EB[y] WE9 WE10 WE14 DATA V1 WE13 Figure 28.
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Electrical Characteristics BCLK WE1 WE2 ADDR Last Valid Addr Address V1 Address V2 WE4 WE3 CS[x] RW WE11 LBA WE12 WE8 WE7 OE WE10 WE9 EB[y] WE18 WE18 ECB WE17 WE17 WE16 WE16 V1 V1+2 Halfword Halfword DATA WE15 V2 Halfword V2+2 Halfword WE15 Figure 29.
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Electrical Characteristics BCLK WE1 ADDR/ Last Valid Addr M_DATA CS[x] RW WE2 WE14 Write Data Address V1 WE13 WE3 WE5 WE4 WE6 Write WE11 WE12 LBA OE EB[y] WE9 WE10 Figure 31. Muxed A/D Mode Timing Diagram for Asynchronous Write Access— WSC=7, LBA=1, LBN=1, LAH=1 BCLK WE1 ADDR/ Last Valid Addr M_DATA WE3 CS[x] WE2 Address V1 WE16 Read Data WE15 WE4 RW WE11 WE12 LBA WE7 OE EB[y] WE9 WE8 WE10 Figure 32.
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Electrical Characteristics SD1 SDCLK SDCLK SD2 SD3 SD4 CS SD5 RAS SD4 SD5 SD4 CAS SD4 SD5 SD5 WE SD6 SD7 ADDR ROW/BA COL/BA SD8 SD10 SD9 DQ Data SD4 DQM Note: CKE is high during the read/write cycle. SD5 Figure 33. SDRAM Read Cycle Timing Diagram Table 31. DDR/SDR SDRAM Read Cycle Timing Parameters ID Parameter Symbol Min Max Unit SD1 SDRAM clock high-level width tCH 3.4 4.1 ns SD2 SDRAM clock low-level width tCL 3.4 4.1 ns SD3 SDRAM clock cycle time tCK 7.
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Electrical Characteristics Table 31. DDR/SDR SDRAM Read Cycle Timing Parameters (continued) ID 1 Parameter Symbol Min Max Unit SD9 Data out hold time1 tOH 1.8 — ns SD10 Active to read/write command period tRC 10 — clock Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see Table 35 and Table 36.
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Electrical Characteristics SD1 SDCLK SDCLK SD2 SD3 SD4 CS SD5 RAS SD11 SD4 CAS SD5 SD4 SD4 WE SD5 SD5 SD12 SD7 SD6 ADDR BA COL/BA ROW / BA SD13 DQ SD14 DATA DQM Figure 34. SDR SDRAM Write Cycle Timing Diagram Table 32. SDR SDRAM Write Timing Parameters ID Parameter Symbol Min Max Unit SD1 SDRAM clock high-level width tCH 3.4 4.1 ns SD2 SDRAM clock low-level width tCL 3.4 4.1 ns SD3 SDRAM clock cycle time tCK 7.5 — ns SD4 CS, RAS, CAS, WE, DQM, CKE setup time tCMS 2.
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Electrical Characteristics Table 32. SDR SDRAM Write Timing Parameters (continued) ID 1 Parameter Symbol Min Max Unit SD13 Data setup time tDS 2.0 — ns SD14 Data hold time tDH 1.3 — ns SD11 and SD12 are determined by SDRAM controller register settings. NOTE SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value.
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Electrical Characteristics Table 33. SDRAM Refresh Timing Parameters ID 1 Parameter Symbol Min Max Unit SD1 SDRAM clock high-level width tCH 3.4 4.1 ns SD2 SDRAM clock low-level width tCL 3.4 4.1 ns SD3 SDRAM clock cycle time tCK 7.5 — ns SD6 Address setup time tAS 1.8 — ns SD7 Address hold time tAH 1.
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Electrical Characteristics SDCLK CS RAS CAS WE ADDR BA SD16 CKE SD16 Don’t care Figure 36. SDRAM Self-Refresh Cycle Timing Diagram NOTE The clock will continue to run unless both CKEs are low. Then the clock will be stopped in low state. Table 34. SDRAM Self-Refresh Cycle Timing Parameters ID SD16 Parameter CKE output delay time Symbol Min Max Unit tCKS 1.8 — ns MCIMX31C/MCIMX31LC Technical Data, Rev. 4.
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Electrical Characteristics SDCLK SDCLK SD20 SD19 DQS (output) SD18 SD17 DQ (output) DQM (output) SD17 SD18 Data Data Data Data Data Data Data Data DM DM DM DM DM DM DM DM SD17 SD17 SD18 SD18 Figure 37. Mobile DDR SDRAM Write Cycle Timing Diagram Table 35. Mobile DDR SDRAM Write Cycle Timing Parameters1 ID 1 Parameter Symbol Min Max Unit SD17 DQ & DQM setup time to DQS tDS 0.95 — ns SD18 DQ & DQM hold time to DQS tDH 0.
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Electrical Characteristics SDCLK SDCLK SD23 DQS (input) SD22 SD21 DQ (input) Data Data Data Data Data Data Data Data Figure 38. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram Table 36. Mobile DDR SDRAM Read Cycle Timing Parameters ID Parameter SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS). SD22 DQS DQ HOLD time from DQS SD23 DQS output access time from SDCLK posedge Symbol Min Max Unit tDQSQ — 0.85 ns tQH 2.3 — ns tDQSCK — 6.
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Electrical Characteristics Table 37. ETM TRACECLK Timing Parameters ID Parameter Min Max Unit Frequency dependent — ns Tcyc Clock period Twl Low pulse width 2 — ns Twh High pulse width 2 — ns Tr Clock and data rise time — 3 ns Tf Clock and data fall time — 3 ns Figure 40 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and Table 38 lists the timing parameters. Figure 40. Trace Data Timing Diagram Table 38.
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Electrical Characteristics 4.3.13 I2C Electrical Specifications This section describes the electrical information of the I2C Module. 4.3.13.1 I2C Module Timing Figure 41 depicts the timing of I2C module. Table 40 lists the I2C module timing parameters where the I/O supply is 2.7 V. 1 I2CLK IC11 IC10 I2DAT IC2 IC10 START IC7 IC4 IC8 IC11 IC6 IC9 IC3 STOP START START IC5 IC1 Figure 41. I2C Bus Timing Diagram Table 40. I2C Module Timing Parameters—I2C Pin I/O Supply=2.
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Electrical Characteristics 4.3.14 IPU—Sensor Interfaces 4.3.14.1 Supported Camera Sensors Table 41 lists the known supported camera sensors at the time of publication. Table 41.
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Electrical Characteristics 4.3.14.2.2 Gated Clock Mode The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See Figure 42. Active Line Start of Frame nth frame n+1th frame SENSB_VSYNC SENSB_HSYNC SENSB_PIX_CLK SENSB_DATA[9:0] invalid invalid 1st byte 1st byte Figure 42. Gated Clock Mode Timing Diagram A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the corresponding signals).
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Electrical Characteristics The timing described in Figure 43 is that of a Motorola sensor. Some other sensors may have a slightly different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC; active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK. 4.3.14.3 Electrical Characteristics Figure 44 depicts the sensor interface timing, and Table 42 lists the timing parameters.
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Electrical Characteristics Table 43.
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Electrical Characteristics • DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. DISPB_D3_VSYNC DISPB_D3_HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n DISPB_D3_HSYNC DISPB_D3_DRDY 1 2 3 m-1 m DISPB_D3_CLK DISPB_D3_DATA Figure 45. Interface Timing Diagram for TFT (Active Matrix) Panels 4.3.15.2.
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Electrical Characteristics End of frame Start of frame IP13 DISPB_D3_VSYNC DISPB_D3_HSYNC DISPB_D3_DRDY IP11 IP15 IP14 IP12 Figure 47. TFT Panels Timing Diagram—Vertical Sync Pulse Table 44 shows timing parameters of signals presented in Figure 46 and Figure 47. Table 44.
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Electrical Characteristics NOTE HSP_CLK is the High-Speed Port Clock, which is the input to the Image Processing Unit (IPU). Its frequency is controlled by the Clock Control Module (CCM) settings. The HSP_CLK frequency must be greater than or equal to the AHB clock frequency. The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF, SDC_BG_POS Registers.
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Electrical Characteristics 3 Display interface clock up time 2 ⋅ DISP3_IF_CLK_UP_WR 1 ⋅ ceil ---------------------------------------------------------------------Tdicu = --- T HSP_CLK_PERIOD 2 HSP_CLK where CEIL(X) rounds the elements of X to the nearest integers towards infinity. 4.3.15.3 Interface to Sharp HR-TFT Panels Figure 49 depicts the Sharp HR-TFT panel interface timing, and Table 46 lists the timing parameters.
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Electrical Characteristics Table 46. Sharp Synchronous Display Interface Timing Parameters—Pixel Level ID Parameter Symbol Value Units IP21 SPL rise time Tsplr (BGXP – 1) * Tdpcp ns IP22 CLS rise time Tclsr CLS_RISE_DELAY * Tdpcp ns IP23 CLS fall time Tclsf CLS_FALL_DELAY * Tdpcp ns IP24 CLS rise and PS fall time Tpsf PS_FALL_DELAY * Tdpcp ns IP25 PS rise time Tpsr PS_RISE_DELAY * Tdpcp ns IP26 REV toggle time Trev REV_TOGGLE_DELAY * Tdpcp ns 4.3.15.
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Electrical Characteristics DISPB_D3_CLK DISPB_D3_HSYNC DISPB_D3_VSYNC DISPB_D3_DRDY DISPB_DATA Cb Y Cr Y Cb Y Cr Pixel Data Timing DISPB_D3_HSYNC 523 524 525 1 2 3 4 5 6 10 DISPB_D3_DRDY DISPB_D3_VSYNC Even Field 261 262 Odd Field 263 264 265 266 267 268 269 273 DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_VSYNC Even Field Odd Field Line and Field Timing - NTSC DISPB_D3_HSYNC 621 622 623 624 625 1 2 3 4 23 DISPB_D3_DRDY DISPB_D3_VSYNC Even Field 308 Odd Field 309 31
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Electrical Characteristics 4.3.15.4.2 Interface to a TV Encoder, Electrical Characteristics The timing characteristics of the TV encoder interface are identical to the synchronous display characteristics. See Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics” on page 55. 4.3.15.5 4.3.15.5.
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Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by CS signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 51.
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Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by WR/RD signals DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR DISPB_RD DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 52.
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Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by CS signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 53.
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Electrical Characteristics DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by ENABLE signal DISPB_BCLK DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Burst access mode with sampling by separate burst clock (BCLK) DISPB_D#_CS DISPB_PAR_RS DISPB_WR (READ/WRITE) DISPB_RD (ENABLE) DISPB_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 54.
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Electrical Characteristics WRITE OPERATION READ OPERATION DISP0_RD_WAIT_ST=00 DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISP0_RD_WAIT_ST=01 DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISP0_RD_WAIT_ST=10 DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA Figure 55. Parallel Interface Timing Diagram—Read Wait States 4.3.15.5.
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Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) IP35, IP33 IP36, IP34 DISPB_D#_CS DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) IP31, IP29 IP32, IP30 read point IP38 IP37 DISPB_DATA (Input) Read Data IP40 IP39 DISPB_DATA (Output) IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 56. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram MCIMX31C/MCIMX31LC Technical Data, Rev. 4.
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Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_D#_CS IP35, IP33 IP36, IP34 DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) IP31, IP29 IP32, IP30 read point IP37 DISPB_DATA (Input) IP38 Read Data IP39 IP40 DISPB_DATA (Output) IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 57. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram MCIMX31C/MCIMX31LC Technical Data, Rev. 4.
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Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) IP35,IP33 IP36, IP34 DISPB_D#_CS DISPB_WR (READ/WRITE) IP31, IP29 IP32, IP30 read point IP37 DISPB_DATA (Input) IP38 Read Data IP39 IP40 DISPB_DATA (Output) IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 58. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram MCIMX31C/MCIMX31LC Technical Data, Rev. 4.
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Electrical Characteristics IP28, IP27 DISPB_PAR_RS DISPB_D#_CS IP35,IP33 IP36, IP34 DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) DISPB_WR (READ/WRITE) IP32, IP30 IP31, IP29 read point IP38 IP37 DISPB_DATA (Input) Read Data IP39 IP40 DISPB_DATA (Output) IP46,IP44 IP47 IP45, IP43 IP42, IP41 Figure 59. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram Table 47.
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Electrical Characteristics Table 47. Asynchronous Parallel Interface Timing Parameters—Access Level (continued) ID Parameter Symbol IP36 Controls hold time for write Tdchw 8 Typ.1 Min. Tdicpw–Tdicdw–1.5 Max. Units — ns Tdicpw–Tdicdw 9 10 Tracc 0 — Tdrp –Tlbd –Tdicur–1.5 ns Troh Tdrp–Tlbd–Tdicdr+1.5 — Tdicpr–Tdicdr–1.5 ns IP39 Write data setup time Tds Tdicdw–1.5 Tdicdw — ns IP40 Write data hold time Tdh Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw — ns Tdicpr–1.5 Tdicpr Tdicpr+1.
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Electrical Characteristics The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers. 4.3.15.5.
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Electrical Characteristics Write DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW RS D7 D6 D5 Preamble D4 D3 D2 D1 D0 Output data DISPB_SD_D (Input) Read DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW RS Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 Input data Figure 61.
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Electrical Characteristics Write DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW D7 D6 D5 Preamble D4 D3 D2 D1 D0 Output data DISPB_SD_D (Input) DISPB_SER_RS Read DISPB_D#_CS 1 display IF clock cycle 1 display IF clock cycle DISPB_SD_D_CLK DISPB_SD_D (Output) RW Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 Input data DISPB_SER_RS Figure 62.
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Electrical Characteristics Figure 63 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries of words.
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Electrical Characteristics Serial Interfaces, Electrical Characteristics 4.3.15.5.4 Figure 64 depicts timing of the serial interface. Table 48 lists the timing parameters at display access level. IP49, IP48 DISPB_SER_RS IP56,IP54 IP57, IP55 DISPB_SD_D_CLK IP51, IP53 IP50, IP52 read point IP59 IP58 DISPB_DATA (Input) Read Data IP60 IP61 DISPB_DATA (Output) IP67,IP65 IP47 IP64, IP66 IP62, IP63 Figure 64. Asynchronous Serial Interface Timing Diagram Table 48.
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Electrical Characteristics Table 48. Asynchronous Serial Interface Timing Parameters—Access Level (continued) ID Parameter Symbol Typ.1 Min. IP56 Controls setup time for write Tdcsw Tdicuw–1.5 Tdicuw IP57 Controls hold time for write Tdchw Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw 8 Max. Units — ns — ns 9 10 Tracc 0 — Tdrp –Tlbd –Tdicur–1.5 ns IP59 Slave device data hold time Troh Tdrp–Tlbd–Tdicdr+1.5 — Tdicpr–Tdicdr–1.5 ns IP60 Write data setup time Tds Tdicdw–1.
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Electrical Characteristics The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers. 4.3.16 Memory Stick Host Controller (MSHC) Figure 65, Figure 66, and Figure 67 depict the MSHC timings, and Table 49 and Table 50 list the timing parameters.
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Electrical Characteristics tSCLKc MSHC_SCLK tBSsu tBSh MSHC_BS tDsu tDh MSHC_DATA (Output) tDd MSHC_DATA (Intput) Figure 67. Transfer Operation Timing Diagram (Parallel) NOTE The Memory Stick Host Controller is designed to meet the timing requirements per Sony's Memory Stick Pro Format Specifications document. Tables in this section details the specifications requirements for parallel and serial modes, and not the MCIMX31C timing. Table 49.
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Electrical Characteristics Table 50. Parallel Interface Timing Parameters1 Standards Signal MSHC_SCLK Parameter Symbol Unit Min Max Cycle tSCLKc 25 — ns H pulse length tSCLKwh 5 — ns L pulse length tSCLKwl 5 — ns Rise time tSCLKr — 10 ns Fall time tSCLKf — 10 ns Setup time tBSsu 8 — ns Hold time tBSh 1 — ns Setup time tDsu 8 — ns Hold time tDh 1 — ns Output delay time tDd — 15 ns MSHC_BS MSHC_DATA 1 Timing is guaranteed for NVCC from 2.7 through 3.
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Electrical Characteristics HCLK HADDR CONTROL HWDATA ADDR 1 CONTROL 1 DATA write 1 HREADY HRESP OKAY A[25:0] ADDR 1 D[15:0] OKAY OKAY DATA write 1 WAIT REG REG OE/WE/IORD/IOWR CE1/CE2 RW POE PSST PSL PSHT Figure 68. Write Accesses Timing Diagram—PSHT=1, PSST=1 MCIMX31C/MCIMX31LC Technical Data, Rev. 4.
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Electrical Characteristics HCLK ADDR 1 HADDR CONTROL CONTROL 1 DATA read 1 RWDATA HREADY HRESP OKAY A[25:0] ADDR 1 OKAY OKAY D[15:0] WAIT REG REG OE/WE/IORD/IOWR CE1/CE2 RW POE PSST PSHT PSL Figure 69. Read Accesses Timing Diagram—PSHT=1, PSST=1 Table 51. PCMCIA Write and Read Timing Parameters Symbol Parameter Min Max Unit PSHT PCMCIA strobe hold time 0 63 clock PSST PCMCIA strobe set up time 1 63 clock PSL PCMCIA strobe length 1 128 clock 4.3.
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Electrical Characteristics 4.3.18.1 PWM Timing Figure 70 depicts the timing of the PWM, and Table 52 lists the PWM timing characteristics. 1 2a 3b System Clock 2b 4b 3a 4a PWM Output Figure 70. PWM Timing Table 52. PWM Output Timing Parameters ID 1 4.3.19 Parameter Min Max Unit 0 ipg_clk MHz 1 System CLK frequency1 2a Clock high time 12.29 — ns 2b Clock low time 9.91 — ns 3a Clock fall time — 0.5 ns 3b Clock rise time — 0.5 ns 4a Output delay time — 9.
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Electrical Characteristics SD4 SD1 SD3 SD2 CLK SD5 SD6 CMD DATA[3:0] Output from SDHC to card SD7 CMD DATA[3:0] Input to SDHC SD8 Figure 71. SDHC Timing Diagram . Table 53.
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Electrical Characteristics The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins. There is no timing relationship between the clock and the data.
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Electrical Characteristics SVEN CLK response RX 1 2 T0 400 clock cycles < 1 < 200 clock cycles 2 < 40000 clock cycles Figure 73. Internal-Reset Card Reset Sequence 4.3.20.2.2 Cards with Active Low Reset The sequence of reset for this kind of card is as follows (see Figure 74): 1. After powerup, the clock signal is enabled on CLK (time T0) 2. After 200 clock cycles, RX must be high. 3.
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Electrical Characteristics 4.3.20.3 Power Down Sequence Power down sequence for SIM interface is as follows: 1. SIMPD port detects the removal of the SIM Card 2. RST goes Low 3. CLK goes Low 4. TX goes Low 5. VEN goes Low Each of this steps is done in one CKIL period (usually 32 kHz). Power down can be started because of a SIM Card removal detection or launched by the processor. Figure 75 and Table 55 show the usual timing requirements for this sequence, with Fckil = CKIL frequency value.
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Electrical Characteristics 4.3.21 SJC Electrical Specifications This section details the electrical characteristics for the SJC module. Figure 76 depicts the SJC test clock input timing. Figure 77 depicts the SJC boundary scan timing, Figure 78 depicts the SJC test access port, Figure 79 depicts the SJC TRST timing, and Table 56 lists the SJC timing parameters. SJ1 SJ2 TCK (Input) SJ2 VM VIH VM VIL SJ3 SJ3 Figure 76.
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Electrical Characteristics TCK (Input) VIH VIL SJ8 TDI TMS (Input) SJ9 Input Data Valid SJ10 TDO (Output) Output Data Valid SJ11 TDO (Output) SJ10 TDO (Output) Output Data Valid Figure 78. Test Access Port Timing Diagram TCK (Input) SJ13 TRST (Input) SJ12 Figure 79. TRST Timing Diagram Table 56.
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Electrical Characteristics Table 56. SJC Timing Parameters (continued) All Frequencies ID Parameter Unit Min Max — 44 ns SJ11 TCK low to TDO high impedance SJ12 TRST assert time 100 — ns SJ13 TRST set-up time to TCK low 40 — ns 1 On cases where SDMA TAP is put in the chain, the max TCK frequency is limited by max ratio of 1:8 of SDMA core frequency to TCK limitation. This implies max frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock. 2 VM - mid point voltage 4.3.
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Electrical Characteristics SS1 SS3 SS5 SS2 SS4 AD1_TXC (Output) SS8 SS6 AD1_TXFS (bl) (Output) SS10 SS12 AD1_TXFS (wl) (Output) SS14 SS15 SS16 SS18 SS17 AD1_TXD (Output) SS43 SS42 SS19 AD1_RXD (Input) Note: SRXD Input in Synchronous mode only SS1 SS3 SS5 SS2 SS4 DAM1_T_CLK (Output) SS6 SS8 DAM1_T_FS (bl) (Output) SS10 SS12 DAM1_T_FS (wl) (Output) SS14 SS15 SS16 SS18 SS17 DAM1_TXD (Output) SS43 SS42 SS19 DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 80.
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Electrical Characteristics Table 57. SSI Transmitter with Internal Clock Timing Parameters ID Parameter Min Max Unit Internal Clock Operation SS1 (Tx/Rx) CK clock period 81.4 — ns SS2 (Tx/Rx) CK clock high period 36.0 — ns SS3 (Tx/Rx) CK clock rise time — 6 ns SS4 (Tx/Rx) CK clock low period 36.0 — ns SS5 (Tx/Rx) CK clock fall time — 6 ns SS6 (Tx) CK high to FS (bl) high — 15.0 ns SS8 (Tx) CK high to FS (bl) low — 15.0 ns SS10 (Tx) CK high to FS (wl) high — 15.
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Electrical Characteristics 4.3.22.2 SSI Receiver Timing with Internal Clock Figure 81 depicts the SSI receiver timing with internal clock, and Table 58 lists the timing parameters.
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Electrical Characteristics Table 58. SSI Receiver with Internal Clock Timing Parameters ID Parameter Min Max Unit Internal Clock Operation SS1 (Tx/Rx) CK clock period 81.4 — ns SS2 (Tx/Rx) CK clock high period 36.0 — ns SS3 (Tx/Rx) CK clock rise time — 6 ns SS4 (Tx/Rx) CK clock low period 36.0 — ns SS5 (Tx/Rx) CK clock fall time — 6 ns SS7 (Rx) CK high to FS (bl) high — 15.0 ns SS9 (Rx) CK high to FS (bl) low — 15.0 ns SS11 (Rx) CK high to FS (wl) high — 15.
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Electrical Characteristics 4.3.22.3 SSI Transmitter Timing with External Clock Figure 82 depicts the SSI transmitter timing with external clock, and Table 59 lists the timing parameters.
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Electrical Characteristics Table 59. SSI Transmitter with External Clock Timing Parameters ID Parameter Min Max Unit External Clock Operation SS22 (Tx/Rx) CK clock period 81.4 — ns SS23 (Tx/Rx) CK clock high period 36.0 — ns SS24 (Tx/Rx) CK clock rise time — 6.0 ns SS25 (Tx/Rx) CK clock low period 36.0 — ns SS26 (Tx/Rx) CK clock fall time — 6.0 ns SS27 (Tx) CK high to FS (bl) high –10.0 15.0 ns SS29 (Tx) CK high to FS (bl) low 10.
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Electrical Characteristics 4.3.22.4 SSI Receiver Timing with External Clock Figure 83 depicts the SSI receiver timing with external clock, and Table 60 lists the timing parameters. SS22 SS26 SS24 SS25 SS23 AD1_TXC (Input) SS30 SS28 AD1_TXFS (bl) (Input) SS32 AD1_TXFS (wl) (Input) SS34 SS35 SS41 SS36 SS40 AD1_RXD (Input) SS22 SS24 SS26 SS23 SS25 DAM1_T_CLK (Input) SS30 SS28 DAM1_T_FS (bl) (Input) SS32 DAM1_T_FS (wl) (Input) SS34 SS35 SS41 SS36 SS40 DAM1_RXD (Input) Figure 83.
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Electrical Characteristics Table 60. SSI Receiver with External Clock Timing Parameters (continued) ID 4.3.23 Parameter Min Max Unit SS28 (Rx) CK high to FS (bl) high –10.0 15.0 ns SS30 (Rx) CK high to FS (bl) low 10.0 — ns SS32 (Rx) CK high to FS (wl) high –10.0 15.0 ns SS34 (Rx) CK high to FS (wl) low 10.0 — ns SS35 (Tx/Rx) External FS rise time — 6.0 ns SS36 (Tx/Rx) External FS fall time — 6.0 ns SS40 SRXD setup time before (Rx) CK low 10.
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Package Information and Pinout 5 Package Information and Pinout This section includes the contact assignment information and mechanical package drawing for the MCIMX31C. MCIMX31C/MCIMX31LC Technical Data, Rev. 4.
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Package Information and Pinout 5.1 MAPBGA Production Package 473 19 x 19 mm, 0.8 mm Pitch This section contains the outline drawing, signal assignment map, and MAPBGA ground/power ID by ball grid location for the 473 19 x 19 mm, 0.8 mm pitch package. 5.1.1 Production Package Outline Drawing–19 x 19 mm 0.8 mm Figure 85. Production Package: Case 1931—0.8 mm Pitch MCIMX31C/MCIMX31LC Technical Data, Rev. 4.
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MAPBGA Signal Assignment–19 × 19 mm 0.8 mm Freescale Semiconductor 5.1.2 1 A GND 2 GND 3 GND 4 B GND GND CSPI2_ STXD4 MISO C GND GND SRXD4 SRXD5 CSPI3_ MISO SFS4 SCK5 ATA_ DMACK ATA_ DIOR CSPI3_ MOSI D STXD5 E F ATA_ CS0 PC_ RST MCIMX31C/MCIMX31LC Technical Data, Rev. 4.
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Package Information and Pinout 5.1.3 Connection Tables–19 x 19 mm 0.8 mm Table 62 shows the device connection list for power and ground, alpha-sorted followed by Table 63 on page 103 which shows the no-connects. Table 64 on page 103 shows the device connection list for signals. 5.1.3.1 Ground and Power ID Locations—19 x 19 mm 0.8 mm Table 62.
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Package Information and Pinout Table 63. 19 x 19 BGA No Connects1 1 5.1.3.2 Signal Ball Location NC N7 NC P7 NC U21 These contacts are not used and must be floated by the user. BGA Signal ID by Ball Grid Location—19 x 19 0.8 mm Table 64.
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Package Information and Pinout Table 64.
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Package Information and Pinout Table 64.
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Product Documentation Table 64.
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Revision History • MCIMX31 Chip Errata (order number MCIMX31CE) The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. ARM Ltd. documentation is available from http://www.arm.com. 7 Revision History Table 65 summarizes revisions to the MCIMX31C/MCIMX31LC Data Sheet since the release of Rev. 3. Table 65.
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How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.