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Spartan-3E FPGA

Starter Kit Board

User Guide

UG230 (v1.2) January 20, 2011

Summary of content (166 pages)

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Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.
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Table of Contents Preface: About This Guide Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R SMA Clock Input or Output Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 UCF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clock Period Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R Writing Data to the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Disabling the Unused LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Chapter 6: VGA Display Port Signal Timing for a 60 Hz, 640x480 VGA Display . . . . . . . . . . . . . . . . . . . .
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R Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Chapter 11: Intel StrataFlash Parallel NOR Flash PROM StrataFlash Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Shared Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Character LCD . . . . . . . . . . . . . . . .
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R UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Chapter 15: Expansion Connectors Hirose 100-pin FX2 Edge Connector (J3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Voltage Supplies to the Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R DDR SDRAM Series Termination and FX2 Connector Differential Termination 158 Appendix B: Example User Constraints File (UCF) 8 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Preface About This Guide This user guide provides basic information on the Spartan-3E FPGA Starter Kit board capabilities, functions, and design. It includes general information on how to use the various peripheral functions included on the board. For detailed reference designs, including VHDL or Verilog source code, please visit the following web link. • Spartan®-3E FPGA Starter Kit Board Reference Page http://www.xilinx.
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R Preface: About This Guide • Chapter 5, “Character LCD Screen,” describes the functionality of the character LCD screen. • Chapter 6, “VGA Display Port,” describes the functionality of the VGA port. • Chapter 7, “RS-232 Serial Ports,” describes the functionality of the RS-232 serial ports. • Chapter 8, “PS/2 Mouse/Keyboard Port,” describes the functionality of the PS/2 mouse and keyboard port. • Chapter 9, “Digital to Analog Converter (DAC),” describes the functionality of the DAC.
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R Chapter 1 Introduction and Overview Thank you for purchasing the Xilinx Spartan®-3E FPGA Starter Kit. You will find it useful in developing your Spartan-3E FPGA application. Choose the Starter Kit Board for Your Needs Depending on specific requirements, choose the Xilinx development board that best suits your needs.
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R Chapter 1: Introduction and Overview Key Components and Features The key features of the Spartan-3E Starter Kit board are: • • Up to 232 user-I/O pins • 320-pin FBGA package • Over 10,000 logic cells • Xilinx 4 Mbit Platform Flash configuration PROM • Xilinx 64-macrocell XC2C64A CoolRunner™ CPLD • 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz • 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash) • 12 Xilinx XC3S500E Spartan-3E FPGA • FPGA configuration stora
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R Design Trade-Offs Design Trade-Offs A few system-level design trade-offs were required in order to provide the Spartan-3E Starter Kit board with the most functionality. Configuration Methods Galore! A typical FPGA application uses a single non-volatile memory to store configuration images. To demonstrate new Spartan-3E FPGA capabilities, the starter kit board has three different configuration memory sources that all need to function well together.
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R Chapter 1: Introduction and Overview 14 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 2 Switches, Buttons, and Knob Slide Switches Locations and Labels The Spartan®-3E FPGA Starter Kit board has four slide switches, as shown in Figure 2-1. The slide switches are located in the lower right corner of the board and are labeled SW3 through SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.
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R Chapter 2: Switches, Buttons, and Knob NET NET NET NET "SW<0>" "SW<1>" "SW<2>" "SW<3>" LOC LOC LOC LOC = = = = "L13" "L14" "H18" "N17" Figure 2-2: | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = LVTTL LVTTL LVTTL LVTTL | | | | PULLUP PULLUP PULLUP PULLUP ; ; ; ; UCF Constraints for Slide Switches Push-Button Switches Locations and Labels The Spartan-3E FPGA Starter Kit board has four momentary-contact push-button switches, shown in Figure 2-3.
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R Rotary Push-Button Switch 3.3V FPGA I/O Pin Push Button BTN_* Signal UG230_c2_03_021206 Figure 2-4: Push-Button Switches Require an Internal Pull-Down Resistor in FPGA Input Pin In some applications, the BTN_SOUTH push-button switch is also a soft reset that selectively resets functions within the FPGA.
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R Chapter 2: Switches, Buttons, and Knob Rotary / Push Button FPGA I/O Pin 3.3V ROT_CENTER Signal UG230_c2_05_021206 Figure 2-6: Push-Button Switches Require Internal Pull-up Resistor in FPGA Input Pin Rotary Shaft Encoder In principal, the rotary shaft encoder behaves much like a cam, connected to central shaft. Rotating the shaft then operates two push-button switches, as shown in Figure 2-7. Depending on which way the shaft is rotated, one of the switches opens before the other.
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R Discrete LEDs direction! See the Rotary Encoder Interface reference design in“Related Resources” for an example.
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R Chapter 2: Switches, Buttons, and Knob Operation Each LED has one side connected to ground and the other side connected to a pin on the Spartan-3E device via a 390Ω current limiting resistor. To light an individual LED, drive the associated FPGA control signal High. UCF Location Constraints Figure 2-11 provides the UCF constraints for the four push-button switches, including the I/O pin assignment, the I/O standard used, the output slew rate, and the output drive current.
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R Chapter 3 Clock Sources Overview As shown in Figure 3-1, the Spartan®-3E FPGA Starter Kit board supports three primary clock input sources, all of which are located below the Xilinx logo, near the Spartan-3E logo. • The board includes an on-board 50 MHz clock oscillator. • Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA can generate clock signals or other high-speed signals on the SMA-style connector.
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R Chapter 3: Clock Sources Clock Connections Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the top of the FPGA. As shown in Table 3-1, each of the clock inputs also optimally connects to an associated DCM.
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R Related Resources NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ; NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ; NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ; Figure 3-2: UCF Location Constraints for Clock Sources Clock Period Constraints The Xilinx ISE® development software uses timing-driven logic placement and routing. Set the clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3 for the on-board 50 MHz clock oscillator.
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R Chapter 3: Clock Sources 24 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 4 FPGA Configuration Options The Spartan®-3E FPGA Starter Kit board supports a variety of FPGA configuration options: • Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the onboard USB interface. The on-board USB-JTAG logic also provides in-system programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD. SPI serial Flash and StrataFlash programming are performed separately.
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R Chapter 4: FPGA Configuration Options 16 Mbit ST Micro SPI Serial Flash Serial Peripheral Interface (SPI) mode Configuration Options USB-based Download/Debug Port PROG_B button, Platform Flash PROM, mode pins Uses standard USB cable 128 Mbit Intel StrataFlash Parallel NOR Flash memory Byte Peripheral Interface (BPI) mode UG230_c4_01_022006 Figure 4-1: Spartan-3E Starter Kit FPGA Configuration Options Configuration Mode Jumper Settings (Header J30) Select between three on-board configuration sou
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R Configuration Mode Jumpers The configuration mode jumpers determine which configuration mode the FPGA uses when power is first applied, or whenever the PROG button is pressed. The DONE pin LED lights when the FPGA successfully finishes configuration. Pressing the PROG button forces the FPGA to restart its configuration process. The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial mode.
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R Chapter 4: FPGA Configuration Options Table 4-1: Spartan-3E Configuration Mode Jumper Settings (Header J30 in Figure 4-2) Configuration Mode BPI Down Mode Pins M2:M1:M0 0:1:1 (see Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM”) JTAG 0:1:0 FPGA Configuration Image Source StrataFlash parallel Flash PROM, starting at address 0x1FF_FFFF and decrementing through address space. The CPLD controls address lines A[24:20] during BPI configuration.
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R Programming the FPGA, CPLD, or Platform Flash PROM via USB Programming the FPGA, CPLD, or Platform Flash PROM via USB As shown in Figure 4-1, page 26, the Spartan-3E Starter Kit includes embedded USB-based programming logic and an USB endpoint with a Type B connector. Via a USB cable connection with the host PC, the iMPACT programming software directly programs the FPGA, the Platform Flash PROM, or the on-board CPLD. Direct programming of the parallel or serial Flash PROMs is not presently supported.
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R Chapter 4: FPGA Configuration Options Programming via iMPACT After successfully compiling an FPGA design using the Xilinx development software, the design can be downloaded using the iMPACT programming software and the USB cable. To begin programming, connect the USB cable to the starter kit board and apply power to the board. Then, double-click Configure Device (iMPACT) from within Project Navigator, as shown in Figure 4-5.
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R Programming the FPGA, CPLD, or Platform Flash PROM via USB If the original FPGA configuration file used the default StartUp clock source, CCLK, iMPACT issues the warning message shown in Figure 4-7. This message can be safely ignored. When downloading via JTAG, the iMPACT software must change the StartUP clock source to use the TCK JTAG clock source.
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R Chapter 4: FPGA Configuration Options UG230_c4_10_022406 Figure 4-9: iMPACT Programming Succeeded, the FPGA’s DONE Pin is High Programming Platform Flash PROM via USB The on-board USB-JTAG circuitry also programs the Xilinx XCF04S serial Platform Flash PROM. The steps provided in this section describe how to set up the PROM file and how to download it to the board to ultimately program the FPGA.
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R Programming the FPGA, CPLD, or Platform Flash PROM via USB UG230_c4_11_022706 Figure 4-10: Set Properties for Bitstream Generator Click Configuration Options as shown in Figure 4-11. Using the Configuration Rate drop list, choose 25 to increase the internal CCLK oscillator to approximately 25 MHz, the fastest frequency when using an XCF04S Platform Flash PROM. Click OK when finished.
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R Chapter 4: FPGA Configuration Options To regenerate the programming file, double-click Generate Programming File, as shown in Figure 4-12. UG230_c4_13_022706 Figure 4-12: Double-Click Generate Programming File Generating the PROM File After generating the program file, double-click Generate PROM, ACE, or JTAG File to launch the iMPACT software, as shown in Figure 4-13.
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R Programming the FPGA, CPLD, or Platform Flash PROM via USB UG230_c4_15_022706 Figure 4-14: Double-Click PROM File Formatter Choose Xilinx PROM as the target PROM type, as shown in Figure 4-15. Select from any of the PROM File Formats; the Intel Hex format (MCS) is popular. Enter the Location of the directory and the PROM File Name. Click Next > when finished.
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R Chapter 4: FPGA Configuration Options The Spartan-3E Starter Kit board has an XCF04S Platform Flash PROM. Select xcf04s from the drop list, as shown in Figure 4-16. Click Add, then click Next >. UG230_c4_17_022706 Figure 4-16: Choose the XCF04S Platform Flash PROM The PROM Formatter then echoes the settings, as shown in Figure 4-17. Click Finish.
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R Programming the FPGA, CPLD, or Platform Flash PROM via USB UG230_c4_19_022706 Figure 4-18: Enter FPGA Configuration Bitstream File(s) When PROM formatting is complete, the iMPACT software presents the present settings by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space consumed by the bitstream. Figure 4-19 shows an example for a single XC3S500E FPGA bitstream stored in an XCF04S Platform Flash PROM.
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R Chapter 4: FPGA Configuration Options To generate the actual PROM file, click Operations  Generate File as shown in Figure 4-20. UG230_c4_21_022706 Figure 4-20: Click Operations  Generate File to Create the Formatted PROM File The iMPACT software indicates that the PROM file was successfully created, as shown in Figure 4-21.
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R Programming the FPGA, CPLD, or Platform Flash PROM via USB UG230_c4_23_022706 Figure 4-22: Switch to Boundary Scan Mode Assign the PROM file to the XCF04S Platform Flash PROM on the JTAG chain, as shown in Figure 4-23. Right-click the PROM icon, then click Assign New Configuration File. Select a previously generated PROM format file and click OK.
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R Chapter 4: FPGA Configuration Options UG230_c4_25_022806 Figure 4-24: Program the XCF04S Platform Flash PROM The programming software again prompts for the PROM type to be programmed. Select xcf04s and click OK, as shown in Figure 4-25. UG230_c4_26_022806 Figure 4-25: Select XCF04S Platform Flash PROM Before programming, choose the programming options available in Figure 4-26.
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R Related Resources UG230_c4_27_022806 Figure 4-26: PROM Programming Options The iMPACT software indicates if programming was successful or not. If programming was successful and the Load FPGA option was left unchecked, push the PROG_B pushbutton switch shown in Figure 4-2, page 26 to force the FPGA to reconfigure from the newly programmed Platform Flash PROM. If the FPGA successfully configures, the DONE LED, also shown in Figure 4-2, lights up.
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R Chapter 4: FPGA Configuration Options 42 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 5 Character LCD Screen Overview The Spartan®-3E FPGA Starter Kit board prominently features a 2-line by 16-character liquid crystal display (LCD). The FPGA controls the LCD via the 4-bit data interface shown in Figure 5-1. Although the LCD supports an 8-bit data interface, the Starter Kit board uses a 4-bit data interface to remain compatible with other Xilinx development boards and to minimize total pin count.
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R Chapter 5: Character LCD Screen Character LCD Interface Signals Table 5-1 shows the interface character LCD interface signals.
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R UCF Location Constraints If the StrataFlash memory is in byte-wide (x8) mode (SF_BYTE = Low), the FPGA application has full simultaneous read/write access to both the LCD and the StrataFlash memory. In byte-wide mode, the StrataFlash memory does not use the SF_D<15:8> data lines. UCF Location Constraints Figure 5-2 provides the UCF constraints for the Character LCD, including the I/O pin assignment and the I/O standard used.
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R Chapter 5: Character LCD Screen Physically, there are 80 total character locations in DD RAM with 40 characters available per line. Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other non-display data. Alternatively, these locations can also store characters that can only displayed using controller’s display shifting functions. The Set DD RAM Address command initializes the address counter before reading or writing to DD RAM.
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R LCD Controller Upper Data Nibble DB3 DB2 DB1 DB0 Lower Data Nibble DB7 DB6 DB5 DB4 Figure 5-4: UG230_c5_02_030306 LCD Character Set The character ROM contains the ASCII English character set and Japanese kana characters. The controller also provides for eight custom character bitmaps, stored in CG RAM. These eight custom characters are displayed by storing character codes 0x00 through 0x07 in a DD RAM location.
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R Chapter 5: Character LCD Screen The CG RAM address counter can either remain constant after read or write operations, or auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry Mode Set command. Figure 5-5 provides an example, creating a special checkerboard character. The custom character is stored in the fourth CG RAM character location, which is displayed when a DD RAM location is 0x03.
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R LCD Character Display Command Set (Continued) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Lower Nibble LCD_RW Upper Nibble LCD_RS Table 5-3: LCD Controller Function Set 0 0 0 0 1 0 1 0 - - Set CG RAM Address 0 0 0 1 A5 A4 A3 A2 A1 A0 Set DD RAM Address 0 0 1 A6 A5 A4 A3 A2 A1 A0 Read Busy Flag and Address 0 1 BF A6 A5 A4 A3 A2 A1 A0 Write Data to CG RAM or DD RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Read Data from CG RAM or DD RAM 1 1 D7 D6 D5 D4 D3
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R Chapter 5: Character LCD Screen This bit either auto-increments or auto-decrements the DD RAM and CG RAM address counter by one location after each Write Data to CG RAM or DD RAM or Read Data from CG RAM or DD RAM command. The cursor or blink position moves accordingly. Bit DB0: (S) Shift 0 Shifting disabled 1 During a DD RAM write operation, shift the entire display value in the direction controlled by Bit DB1 (I/D). Appears as though the cursor position remains constant and the display moves.
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R LCD Controller Table 5-4: Shift Patterns According to S/C and R/L Bits DB3 DB2 (S/C) (R/L) Operation 0 0 Shift the cursor position to the left. The address counter is decremented by one. 0 1 Shift the cursor position to the right. The address counter is incremented by one. 1 0 Shift the entire display to the left. The cursor follows the display shift. The address counter is unchanged. 1 1 Shift the entire display to the right. The cursor follows the display shift.
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R Chapter 5: Character LCD Screen After the write operation, the address is automatically incremented or decremented by 1 according to the Entry Mode Set command. The entry mode also determines display shift. Execution Time: 40 μs Read Data from CG RAM or DD RAM Read data from DD RAM if the command follows a previous Set DD RAM Address command, or read data from CG RAM if the command follows a previous Set CG RAM Address command.
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R Operation The data values on SF_D<11:8>, and the register select (LCD_RS) and the read/write (LCD_RW) control signals must be set up and stable at least 40 ns before the enable LCD_E goes High. The enable signal must remain High for 230 ns or longer—the equivalent of 12 or more clock cycles at 50 MHz. In many applications, the LCD_RW signal can be tied Low permanently because the FPGA generally has no reason to read information from the display.
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R Chapter 5: Character LCD Screen • Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock cycles) after issuing this command. Writing Data to the Display To write data to the display, specify the start address, followed by one or more data values. Before writing any data, issue a Set DD RAM Address command to specify the initial 7-bit address in the DD RAM. See Figure 5-3 for DD RAM locations. Write data to the display using a Write Data to CG RAM or DD RAM command.
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R Chapter 6 VGA Display Port The Spartan®-3E FPGA Starter Kit board includes a VGA display port via a DB15 connector. Connect this port directly to most PC monitors or flat-panel LCDs using a standard monitor cable. As shown in Figure 6-1, the VGA connector is the left-most connector along the top of the board.
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R Chapter 6: VGA Display Port Table 6-1: 3-Bit Display Color Codes VGA_RED VGA_GREEN VGA_BLUE Resulting Color 0 0 0 Black 0 0 1 Blue 0 1 0 Green 0 1 1 Cyan 1 0 0 Red 1 0 1 Magenta 1 1 0 Yellow 1 1 1 White VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA). The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode.
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R Signal Timing for a 60 Hz, 640x480 VGA Display pixel 0,0 pixel 0,639 640 pixels are displayed each time the beam traverses the screen VGA Display Current through the horizontal deflection coil pixel 479,0 pixel 479,639 Retrace: No information is displayed during this time Stable current ramp: Information is displayed during this time Total horizontal time Horizontal display time time "front porch" retrace time "front porch" HS Horizontal sync signal sets the retrace frequency "back porch" U
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R Chapter 6: VGA Display Port As shown in Figure 6-2, the VGA controller generates the horizontal sync (HS) and vertical sync (VS) timings signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the refresh frequency of the display, or the frequency at which all information on the display is redrawn.
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R UCF Location Constraints UCF Location Constraints Figure 6-4 provides the UCF constraints for the VGA display port, including the I/O pin assignment, the I/O standard used, the output slew rate, and the output drive current.
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R Chapter 6: VGA Display Port 60 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 7 RS-232 Serial Ports Overview As shown in Figure 7-1, the Spartan®-3E FPGA Starter Kit board has two RS-232 serial ports: a female DB9 DCE connector and a male DTE connector. The DCE-style port connects directly to the serial port connector available on most personal computers and workstations via a standard straight-through serial cable. Null modem, gender changers, or crossover cables are not required.
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R Chapter 7: RS-232 Serial Ports Figure 7-1 shows the connection between the FPGA and the two DB9 connectors. The FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device, which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise, the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A series resistor between the Maxim output pin and the FPGA’s RXD pin protects against accidental logic conflicts.
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R Chapter 8 PS/2 Mouse/Keyboard Port The Spartan®-3E FPGA Starter Kit board includes a PS/2 mouse/keyboard port and the standard 6-pin mini-DIN connector, labeled J14 on the board. Figure 8-1 shows the PS/2 connector, and Table 8-1 shows the signals on the connector. Only pins 1 and 5 of the connector attach to the FPGA.
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R Chapter 8: PS/2 Mouse/Keyboard Port organized differently for a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard. The PS/2 bus timing appears in Table 8-2 and Figure 8-2. The clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at logic High.
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R ESC 76 `~ 0E 1! 16 TA B 0D Keyboard F1 05 F2 06 2@ 1E 3# 26 Q 15 Caps Lock 58 Shift 12 W 1D A 1C F3 04 4$ 25 E 24 S 1B Z 1Z Ctrl 14 F4 0C X 22 F5 03 5% 2E R 2D D 23 6^ 36 T 2C F 2B C 21 F6 0B 7& 3D Y 35 G 34 V 2A F7 83 8* 3E U 3C H 33 B 32 Alt 11 F8 0A 9( 46 I 43 J 3B N 31 0) 45 O 44 K 42 M 3A F10 09 -_ 4E =+ 55 P 4D L 4B ,< 41 F9 01 [{ 54 ;: 4C >.
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R Chapter 8: PS/2 Mouse/Keyboard Port Mouse A mouse generates a clock and data signal when moved; otherwise, these signals remain High, indicating the Idle state. Each time the mouse is moved, the mouse sends three 11-bit words to the host. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 data bits (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit.
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R Voltage Supply Voltage Supply The PS/2 port on the Spartan-3E FPGA Starter Kit board is powered by 5V. Although the Spartan-3E FPGA is not a 5V-tolerant device, it can communicate with a 5V device using series current-limiting resistors, as shown in Figure 8-1. UCF Location Constraints Figure 8-6 provides the UCF constraints for the PS/2 port connecting, including the I/O pin assignment and the I/O standard used.
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R Chapter 8: PS/2 Mouse/Keyboard Port 68 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 9 Digital to Analog Converter (DAC) The Spartan®-3E FPGA Starter Kit board includes an SPI-compatible, four-channel, serial Digital-to-Analog Converter (DAC). The DAC device is a Linear Technology LTC2624 quad DAC with 12-bit unsigned resolution. The four outputs from the DAC appear on the J5 header, which uses the Digilent 6-pin Peripheral Module format. The DAC and the header are located immediately above the Ethernet RJ-45 connector, as shown in Figure 9-1.
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R Chapter 9: Digital to Analog Converter (DAC) LTC 2624 DAC Header J5 REF A 3.3V DAC A VOUTA A DAC B VOUTB B DAC C VOUTC C DAC D VOUTD D 12 REF B 12 REF C 2.5V 12 REF D 12 Spartan-3E FPGA (N10) (T4) (N8) (U16) (P8) SPI_MOSI DAC_CS SPI_SCK DAC_CLR CS/LD SCK SPI Control Interface VCC (3.3V) CLR SPI_MISO Figure 9-2: GND SDO SDI UG230_c9_02_021806 Digital-to-Analog Connection Schematics Interface Signals Table 9-1 lists the interface signals between the FPGA and the DAC.
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R SPI Communication Table 9-2: Disabled Devices on the SPI Bus Signal Disabled Device Disable Value SPI_SS_B SPI serial Flash 1 AMP_CS Programmable pre-amplifier 1 AD_CONV Analog-to-Digital Converter (ADC) 0 SF_CE0 StrataFlash Parallel Flash PROM 1 FPGA_INIT_B Platform Flash PROM 0 SPI Communication Details Figure 9-3 shows a detailed example of the SPI bus timing. Each bit is transmitted or received relative to the SPI_SCK clock signal.
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R Chapter 9: Digital to Analog Converter (DAC) SPI_MISO SPI_MOSI 0 31 Slave: LTC2624 DAC x x x x 0 1 2 3 4 5 6 7 8 9 10 11 a0 a1 a2 a3 c0 c1 c2 c3 x x x x x x x x DAC_CS Master Spartan-3E SPI_SCK FPGA lsb msb Don’t Care Don’t Care 12-bit Unsigned DATA a3 0 0 0 0 1 Figure 9-4: a2 0 0 0 0 1 a1 0 0 1 1 1 COMMAND a0 0 1 0 1 1 ADDRESS DAC A DAC B DAC C DAC D All UG230_c9_04_021806 SPI Communications Protocol to LTC2624 DAC The FPGA first sends eight dummy or “don’t care” bits, followed by a 4-b
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R UCF Location Constraints UCF Location Constraints Figure 9-5 provides the UCF constraints for the DAC interface, including the I/O pin assignment and the I/O standard used.
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R Chapter 9: Digital to Analog Converter (DAC) 74 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 10 Analog Capture Circuit The Spartan®-3E FPGA Starter Kit board includes a two-channel analog capture circuit, consisting of a programmable scaling pre-amplifier and an analog-to-digital converter (ADC), as shown in Figure 10-1. Analog inputs are supplied on the J7 header.
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R Chapter 10: Analog Capture Circuit Header J7 REFAB (3.3V) REFCD (2.5V) LTC 6912-1 AMP VINA LTC 1407A-1 ADC A VINB A/D Channel 0 B 14 A/D Channel 1 GND VCC (3.3V) 14 REF = 1.65V Spartan-3E FPGA SPI_MOSI (N10) (T4) (E18) (N7) AMP_CS 0 1 2 3 0 1 2 3 B GAIN CS/LD A GAIN (U16) SPI_SCK SCK SPI Control Interface SCK SPI Control Interface SHDN CONV (P7) (P11) AMP_SHDN DIN DOUT 0 ... 13 0 ...
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R Programmable Pre-Amplifier Finally, the ADC presents a 14-bit, two’s complement digital output. A 14-bit, two’s complement number represents values between -213 and 213-1. Therefore, the quantity is scaled by 8192, or 213. See “Programmable Pre-Amplifier” to control the GAIN settings on the programmable pre-amplifier. The reference design files provide more information on converting the voltage applied on VINA or VINB to a digital representation (see “Related Resources,” page 81).
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R Chapter 10: Analog Capture Circuit Table 10-2: Programmable Gain Settings for Pre-Amplifier (Continued) A3 A2 A1 A0 Input Voltage Range B3 B2 B1 B0 Minimum Maximum -5 0 0 1 1 1.4 1.9 -10 0 1 0 0 1.525 1.775 -20 0 1 0 1 1.5875 1.7125 -50 0 1 1 0 1.625 1.675 -100 0 1 1 1 1.6375 1.6625 Gain SPI Control Interface Figure 10-3 highlights the SPI-based communications interface with the amplifier.
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R Analog to Digital Converter (ADC) The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency. UCF Location Constraints Figure 10-5 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used.
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R Chapter 10: Analog Capture Circuit SPI_MISO Slave: LTC1407A-1 A/D Converter Spartan-3E FPGA Master D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 AD_CONV SPI_SCK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Z Sample point Z Z Channel 1 Channel 0 Converted data is presented with a latency of one sample. The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV. The converted values is then presented after the next AD_CONV pulse.
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R Disable Other Devices on the SPI Bus to Avoid Contention Disable Other Devices on the SPI Bus to Avoid Contention The SPI bus signals are shared by other devices on the board. It is vital that other devices are disabled when the FPGA communicates with the AMP or ADC to avoid bus contention. Table 10-4 provides the signals and logic values required to disable the other devices. Although the StrataFlash PROM is a parallel device, its least-significant data bit is shared with the SPI_MISO signal.
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R Chapter 10: Analog Capture Circuit 82 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 11 Intel StrataFlash Parallel NOR Flash PROM As shown in Figure 11-1, the Spartan®-3E FPGA Starter Kit boards includes a 128 Mbit (16 Mbyte) Intel StrataFlash parallel NOR Flash PROM. As indicated, some of the StrataFlash connections are shared with other components on the board.
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R Chapter 11: Intel StrataFlash Parallel NOR Flash PROM • Stores MicroBlaze processor code in the StrataFlash device and shadows the code into the DDR memory before executing the code. • Stores non-volatile data from the FPGA. StrataFlash Connections Table 11-1 shows the connections between the FPGA and the StrataFlash device. Although the XC3S500E FPGA only requires just slightly over 2 Mbits per configuration image, the FPGA-to-StrataFlash interface on the board support up to a 256 Mbit StrataFlash.
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R StrataFlash Connections Table 11-1: Address Category FPGA-to-StrataFlash Connections StrataFlash Signal Name FPGA Pin Number SF_A24 A11 SF_A23 N11 SF_A22 V12 SF_A21 V13 SF_A20 T12 SF_A19 V15 SF_A18 U15 SF_A17 T16 SF_A16 U18 SF_A15 T17 SF_A14 R18 SF_A13 T18 SF_A12 L16 SF_A11 L15 SF_A10 K13 SF_A9 K12 SF_A8 K15 SF_A7 K14 SF_A6 J17 SF_A5 J16 SF_A4 J15 SF_A3 J14 SF_A2 J12 SF_A1 J13 SF_A0 H17 Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 11: Intel StrataFlash Parallel NOR Flash PROM Table 11-1: Control Data Category FPGA-to-StrataFlash Connections StrataFlash Signal Name FPGA Pin Number SF_D15 T8 SF_D14 R8 SF_D13 P6 SF_D12 M16 SF_D11 M15 SF_D10 P17 SF_D9 R16 SF_D8 R15 SF_D7 N9 SF_D6 M9 SF_D5 R9 SF_D4 U9 SF_D3 V9 SF_D2 R10 SF_D1 P10 SPI_MISO N10 Bit 0 of data byte and 16-bit halfword. Connects to FPGA pin D0/DIN to support the BPI configuration.
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R Shared Connections Shared Connections Besides the connections to the FPGA, the StrataFlash memory shares some connections to other components. Character LCD The character LCD uses a four-bit data interface. The display data connections are also shared with the SF_D<11:8> signals on the StrataFlash PROM. As shown in Table 11-2, the FPGA controls access to the StrataFlash PROM or the character LCD using the SF_CE0 and LCD_RW signals.
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R Chapter 11: Intel StrataFlash Parallel NOR Flash PROM UCF Location Constraints Address Figure 11-2 provides the UCF constraints for the StrataFlash address pins, including the I/O pin assignment and the I/O standard used.
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R Setting the FPGA Mode Select Pins Control Figure 11-4 provides the UCF constraints for the StrataFlash control pins, including the I/O pin assignment and the I/O standard used.
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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM 90 www.xilinx.com R Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 12 SPI Serial Flash The Spartan®-3E FPGA Starter Kit board includes a STMicroelectronics M25P16 16 Mbit SPI serial Flash, useful in a variety of applications. The SPI Flash provides an alternative means to configure the FPGA—a new feature of Spartan-3E FPGAs as shown in Figure 12-1. The SPI Flash is also available to the FPGA after configuration for a variety of purposes, such as: • Simple non-volatile data storage • Storage for identifier codes, serial numbers, IP addresses, etc.
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R Chapter 12: SPI Serial Flash Configuring from SPI Flash To configure the FPGA from SPI Flash, the FPGA mode select pins must be set appropriately and the SPI Flash must contain a valid configuration image.
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R Configuring from SPI Flash Creating an SPI Serial Flash PROM File The following steps describe how to format an FPGA bitstream for an SPI Serial Flash PROM. Setting the Configuration Clock Rate The FPGA supports a 12 MHz configuration clock rate when connected to an M25P16 SPI serial Flash. Set the Properties for Generate Programming File so that the Configuration Rate is 12, as shown in Figure 12-5.
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R Chapter 12: SPI Serial Flash Formatting an SPI Flash PROM File After generating the program file, double-click Generate PROM, ACE, or JTAG File to launch the iMPACT software, as shown in Figure 12-6. UG230_c15_05_030206 Figure 12-6: Double-Click Generate PROM, ACE, or JTAG File After iMPACT starts, double-click PROM File Formatter, as shown in Figure 12-7. UG230_c15_06_030206 Figure 12-7: Double-Click PROM File Formatter Choose 3rd Party SPI PROM as the target PROM type, as shown in Figure 12-8.
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R Configuring from SPI Flash UG230_c15_07_030206 Figure 12-8: Choose the PROM Target Type, the, Data Format, and File Location The Spartan-3E Starter Kit board has a 16 Mbit SPI serial Flash PROM. Select 16M from the drop list, as shown in Figure 12-9. Click Next >. UG230_c15_08_030206 Figure 12-9: Choose 16M The PROM Formatter then echoes the settings, as shown in Figure 12-10. Click Finish. Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 www.xilinx.
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R Chapter 12: SPI Serial Flash UG230_c15_09_030206 Figure 12-10: Click Finish after Entering PROM Formatter Settings The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream file. As shown in Figure 12-11, click OK to start selecting files. Select an FPGA bitstream file (*.bit). Choose No after selecting the last FPGA file. Finally, click OK to continue.
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R Configuring from SPI Flash To generate the actual PROM file, click Operations  Generate File as shown in Figure 12-13. UG230_c15_12_030206 Figure 12-13: Click Operations  Generate File to Create the Formatted PROM File As shown in Figure 12-14, the iMPACT software indicates that the PROM file was successfully created. The PROM Formatter creates an output file based on the settings shown in Figure 12-8. In this example, the output file is called MySPIFlash.mcs.
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R Chapter 12: SPI Serial Flash • Via the FPGA’s JTAG chain, use a JTAG tool to program the SPI Flash connected to the FPGA. See the link to the Universal Scan SPI Flash programming tutorial in “Related Resources,” page 103. Downloading the SPI Flash The following steps describe how to download the SPI Flash PROM.
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R Configuring from SPI Flash a) JTAG3 Parallel Connector b) Parallel Cable III or Parallel Cable IV with Flying Leads UG230_c15_14_030206 Figure 12-15: Table 12-2: Attaching a JTAG Parallel Programming Cable to the Board Cable Connections to J12 Header Cable and Labels Connections J12 Header Label SEL SDI SDO SCK GND VCC JTAG3 Cable Label TMS TDI TDO TCK GND VCC Flying Leads Label TMS/ PROG TDI/ DIN TDO/ DONE TCK/ CCLK GND/ GND VREF/ VREF Insert Jumper on JP8 and Hold PROG_B L
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R Chapter 12: SPI Serial Flash After programming the SPI Flash, remove jumper JP8, as shown in Figure 12-16a. If properly programmed, the FPGA then configures itself from the SPI Flash PROM and the DONE LED lights. The DONE LED is shown in Figure 12-3. Additional Design Details Figure 12-17 provides additional details of the SPI Flash interface used on the Spartan-3E Starter Kit board. In most applications, this interface is as simple as that shown in Figure 12-1.
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R Additional Design Details Table 12-3: Disable Other Devices on SPI Bus Signal Disabled Device Disable Value DAC_CS Digital-to-Analog Converter (DAC) 1 AMP_CS Programmable Pre-Amplifier 1 AD_CONV Analog-to-Digital Converter (ADC) 0 SF_CE0 StrataFlash Parallel Flash PROM 1 FPGA_INIT_B Platform Flash PROM 0 Other SPI Flash Control Signals The M25P16 SPI Flash has two additional control inputs.
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R Chapter 12: SPI Serial Flash be left floating. Why support multiple packages? In a word, flexibility. The multi-package layout provides ... • Density migration between smaller- and larger-density SPI Flash PROMs. Not all SPI Flash densities are available in all packages. The SPI Flash migration strategy follows nicely with the pinout migration provided by Xilinx FPGAs. • Consistent configuration PROM layout when migrating between FPGA densities.
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R Related Resources Related Resources • Xilinx Parallel Cable IV with Flying Leads • Digilent JTAG3 Programming Cable http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,395&Cat=5#JTAG3 • STMicroelectronics M25P16 SPI Serial Flash Data Sheet http://www.numonyx.com/Documents/Datasheets/M25P16.pdf • PicoBlaze SPI Serial Flash Programmer, via RS-232 (Reference Design) http://www.xilinx.com/s3estarter • Using Serial Flash on the Spartan-3E Starter Kit Board (Reference Design) http://www.xilinx.
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R Chapter 12: SPI Serial Flash 104 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 13 DDR SDRAM The Spartan®-3E FPGA Starter Kit boards includes a 512 Mbit (32M x 16) Micron Technology DDR SDRAM (MT46V32M16) with a 16-bit data interface, as shown in Figure 13-1. All DDR SDRAM interface pins connect to the FPGA’s I/O Bank 3 on the FPGA. I/O Bank 3 and the DDR SDRAM are both powered by 2.5V, generated by an LTC3412 regulator from the board’s 5V supply input. The 1.25V reference voltage, common to the FPGA and DDR SDRAM, is generated using a resistor voltage divider from the 2.
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R Chapter 13: DDR SDRAM All DDR SDRAM interface signals are terminated. The differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O Bank 0 to have best access to one of the FPGA’s Digital Clock Managers (DCMs). This path is required when using the MicroBlaze OPB DDR controller. The MicroBlaze OPB DDR SDRAM controller IP core documentation is also available from within the EDK 8.1i development software (see “Related Resources,” page 109).
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R DDR SDRAM Connections Table 13-1: Control Data Category FPGA-to-DDR SDRAM Connections (Continued) DDR SDRAM Signal Name FPGA Pin Number SD_DQ15 H5 SD_DQ14 H6 SD_DQ13 G5 SD_DQ12 G6 SD_DQ11 F2 SD_DQ10 F1 SD_DQ9 E1 SD_DQ8 E2 SD_DQ7 M6 SD_DQ6 M5 SD_DQ5 M4 SD_DQ4 M3 SD_DQ3 L4 SD_DQ2 L3 SD_DQ1 L1 SD_DQ0 L2 SD_BA1 K6 SD_BA0 K5 SD_RAS C1 SD_CAS C2 SD_WE D1 SD_CK_N J4 SD_CK_P J5 SD_CKE K3 Active-High clock enable input SD_CS K4 Active-Low chip select input
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R Chapter 13: DDR SDRAM UCF Location Constraints Address Figure 13-2 provides the User Constraint File (UCF) constraints for the DDR SDRAM address pins, including the I/O pin assignment and the I/O standard used.
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R Related Resources Control Figure 13-4 provides the User Constraint File (UCF) constraints for the DDR SDRAM control pins, including the I/O pin assignment and the I/O standard used.
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R Chapter 13: DDR SDRAM 110 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 14 10/100 Ethernet Physical Layer Interface The Spartan®-3E FPGA Starter Kit board includes a Standard Microsystems LAN83C185 10/100 Ethernet physical layer (PHY) interface and an RJ-45 connector, as shown in Figure 14-1. With an Ethernet Media Access Controller (MAC) implemented in the FPGA, the board can optionally connect to a standard Ethernet network. All timing is controlled from an on-board 25 MHz crystal oscillator.
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R Chapter 14: 10/100 Ethernet Physical Layer Interface Ethernet PHY Connections The FPGA connects to the LAN83C185 Ethernet PHY using a standard Media Independent Interface (MII), as shown in Figure 14-2. A more detailed description of the interface signals, including the FPGA pin number, appears in Table 14-1.
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R MicroBlaze Ethernet IP Cores Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY (Continued) Signal Name FPGA Pin Number E_RX_CLK V3 Receive Clock. 25 MHz in 100Base-TX mode, and 2.5 MHz in 10Base-T mode. E_CRS U13 Carrier Sense E_COL U6 MII Collision Detect. E_MDC P9 Management Clock. Serial management clock. E_MDIO U5 Management Data Input/Output. Function MicroBlaze Ethernet IP Cores The Ethernet PHY is primarily intended for use with MicroBlaze applications.
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R Chapter 14: 10/100 Ethernet Physical Layer Interface The hardware evaluation versions of the Ethernet MAC cores operate for approximately eight hours in silicon before timing out. To order the full version of the core, visit the Xilinx website at: http://www.xilinx.com/products/ipcenter/OPB_10_100_Lite.htm UCF Location Constraints Figure 14-4 provides the UCF constraints for the 10/100 Ethernet PHY interface, including the I/O pin assignment and the I/O standard used.
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R Chapter 15 Expansion Connectors The Spartan®-3E FPGA Starter Kit board provides a variety of expansion connectors for easy interface flexibility to other off-board components.
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R Chapter 15: Expansion Connectors Hirose 100-pin Expansion Connector (J3) Spartan-3E FPGA (See Table) (See Table) (C3) (C15) (E10) (D10) (D9) FX2_IO<34:1> FX2_IP<38:35> FX2_IO<39> FX2_IP<40> FX2_CLKIN FX2_CLKOUT FX2_CLKIO (See Table) (See Table) (A.44) (A.45) (B.46) (A.47) (B.48) Bank 0 Supply (JP9) 2.5V 3.3V 5.
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R Table 15-1: Hirose 100-pin FX2 Edge Connector (J3) Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3) Signal Name FPGA Pin Shared Header Connections FX2 Connector LED A (top) J1 J2 JP4 J6 FPGA Pin B (bottom) Signal Name VCCO_0 1 1 SHIELD VCCO_0 2 2 TMS_B 3 3 TDO_XC2C JTSEL 4 4 TCK_B TDO_FX2 5 5 GND GND GND GND FX2_IO1 B4 ◆ ◆ 6 6 GND GND FX2_IO2 A4 ◆ ◆ 7 7 GND GND FX2_IO3 D5 ◆ ◆ 8 8 GND GND FX2_IO4 C5 ◆ ◆ 9 9 GND GND FX2_IO5
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R Chapter 15: Expansion Connectors Table 15-1: Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3) (Continued) Shared Header Connections FX2 Connector LED A (top) Signal Name FPGA Pin FX2_IO30 C4 35 35 GND GND FX2_IO31 B11 36 36 GND GND FX2_IO32 A11 37 37 GND GND FX2_IO33 A8 38 38 GND GND FX2_IO34 G9 39 39 GND GND FX2_IP35 D12 40 40 GND GND FX2_IP36 C12 41 41 GND GND FX2_IP37 A15 42 42 GND GND FX2_IP38 B15 43 43 GND GND FX2_IO39 C3 4
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R Table 15-2: Hirose 100-pin FX2 Edge Connector (J3) Differential I/O Pairs Differential Pair 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Signal Name FPGA Pins FPGA Pin Name Direction DIFF_TERM FX2_IO1 B4 IO_L24N_0 I/O Yes FX2_IO2 A4 IO_L24P_0 I/O Yes FX2_IO3 D5 IO_L23N_0 I/O Yes FX2_IO4 C5 IO_L23P_0 I/O Yes FX2_IO5 A6 IO_L20N_0 I/O Yes FX2_IO6 B6 IO_L20P_0 I/O Yes FX2_IO7 E7 IO_L19N_0 I/O Yes FX2_IO8 F7 IO_L19P_0 I/O Yes FX2_IO9 D7 IO_L18N_0 I/O Yes FX2_IO1
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R Chapter 15: Expansion Connectors Using Differential Inputs LVDS and RSDS differential inputs require input termination. Two options are available. The first option is to use external termination resistors, as shown in Figure 15-3a. The board provides landing pads for external 100Ω termination resistors. The resistors are not loaded on the board as shipped. The resistor reference designators are labeled on the silkscreen, as listed in Table 15-2.
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R Hirose 100-pin FX2 Edge Connector (J3) UG230_c12_05_022406 Figure 15-5: Location of Termination Resistor Pads on Bottom Side of Board Using Differential Outputs Differential input signals do not require any special voltage. LVDS and RSDS differential outputs signals, on the other hand, require a 2.5V supply on I/O Bank 0. The board provides the option to power I/O Bank 0 with either 3.3V or 2.5V. Figure 15-1, page 115 highlights the location of jumper JP9.
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R Chapter 15: Expansion Connectors # ==== FX2 Connector (FX2) ==== NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ; NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # These four connections are shared with the J1 6-pin accessory header NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
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R Six-Pin Accessory Headers Six-Pin Accessory Headers The 6-pin accessory headers provide easy I/O interface expansion using the various Digilent Peripheral Modules (see “Related Resources,” page 126). The location of the 6-pin headers is provided in Figure 15-1, page 115. Header J1 The J1 header, shown in Figure 15-8, is the top-most 6-pin connector along the right edge of the board. It uses a female 6-pin 90° socket. Four FPGA pins connect to the J1 header, FX2_IO<4:1>.
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R Chapter 15: Expansion Connectors Header J4 The J4 header, shown in Figure 15-10, is located immediately to the left of the J1 header. It uses a 6-pin header consisting of 0.1-inch centered stake pins. Four FPGA pins connect to the J4 header, FX2_IO<12:9>. These four signals are also shared with the Hirose FX2 connector. The board supplies 3.3V to the accessory board mounted in the J4 socket on the bottom pin. J4 Spartan-3E FPGA (D7) (C7) FX2_IO9 FX2_IO10 (F8) FX2_IO11 (E8) FX2_IO12 GND 3.
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R Connectorless Debugging Port Landing Pads (J6) Connectorless Debugging Port Landing Pads (J6) Landing pads for a connectorless debugging port are provided as header J6, shown in Figure 15-1, page 115. There is no physical connector on the board. Instead a connectorless probe, such as those available from Agilent, provides an interface to a logic analyzer. This debugging port is intended primarily for the Xilinx ChipScope Pro software with the Agilent’s FPGA Dynamic Probe.
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R Chapter 15: Expansion Connectors Related Resources • Hirose connectors http://www.hirose-connectors.com/ • FX2 Series Connector Data Sheet http://www.hirose.co.jp/cataloge_hp/e57220088.pdf • Digilent, Inc. Peripheral Modules http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9 • Xilinx ChipScope Pro Tool http://www.xilinx.com/tools/cspro.htm • Agilent B4655A FPGA Dynamic Probe for Logic Analyzer http://cp.literature.agilent.com/litweb/pdf/5989-0423EN.
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R Chapter 16 XC2C64A CoolRunner-II CPLD The Spartan®-3E FPGA Starter Kit board includes a Xilinx XC2C64A CoolRunner™-II CPLD. The CPLD is user programmable and available for customer applications. Portions of the CPLD are reserved to coordinate behavior between the various FPGA configuration memories, namely the Xilinx Platform Flash PROM and the Intel StrataFlash PROM. Consequently, the CPLD must provide the following functions in addition to the user application.
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R Chapter 16: XC2C64A CoolRunner-II CPLD 3.
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R UCF Location Constraints UCF Location Constraints There are two sets of constraints listed below–one for the Spartan-3E FPGA and one for the XC2C64A CoolRunner-II CPLD. FPGA Connections to CPLD Figure 16-2 provides the UCF constraints for the FPGA connections to the CPLD , including the I/O pin assignment and the I/O standard used.
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R Chapter 16: XC2C64A CoolRunner-II CPLD Related Resources • CoolRunner-II CPLD Family Data Sheet http://www.xilinx.com/support/documentation/data_sheets/ds090.pdf • XC2C64A CoolRunner-II CPLD Data Sheet http://www.xilinx.com/support/documentation/data_sheets/ds311.pdf • Default XC2C64A CPLD Design for Spartan-3E Starter Kit Board http://www.xilinx.com/s3estarter 130 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Chapter 17 DS2432 1-Wire SHA-1 EEPROM The Spartan®-3E FPGA Starter Kit board includes a Maxim DS2432 serial EEPROM with an integrated SHA-1 engine. As shown in Figure 17-1, the DS2432 EEPROM uses the Maxim 1-Wire interface, which as the name implies, cleverly uses a single wire for power and serial communication. The DS2432 EEPROM offers one of many possible means to copy-protect the FPGA configuration bitstream, making cloning difficult.
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R Chapter 17: DS2432 1-Wire SHA-1 EEPROM 132 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Appendix A Schematics This appendix provides the following circuit board schematics: • “FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header” • “RS-232 Ports, VGA Port, and PS/2 Port” • “Ethernet PHY, Magnetics, and RJ-11 Connector” • “Voltage Regulators” • “FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections” • “FPGA I/O Banks 0 and 1, Oscillators” • “FPGA I/O Banks 2 and 3” • “Power Supply Decoupling” • “XC2C64A CoolRunner-II CPLD” •
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R Appendix A: Schematics FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header Headers J1, J2, and J4 are six-pin connectors compatible with the Digilent Accessory board format. Headers J3A and J3B are the connections to the FX2 expansion connector located along the right edge of the board. Header J5 provides the four analog outputs from the Digital-to-Analog Converter (DAC). Header J6 is the landing pad for an Agilent or Tektronix connectorless probe.
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R FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header UG230_Aa_01_021806 Figure A-1: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 1 www.xilinx.
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R Appendix A: Schematics RS-232 Ports, VGA Port, and PS/2 Port IC2 is the Maxim LVTTL to RS-232 level converter. One of the serial channels connects to a female DB9 DCE connector (J9) and the other connects to a male DB9 DTE connector (J10). See Chapter 7, “RS-232 Serial Ports,” for additional information. Connector J14 is a PS/2-style mouse/keyboard connector, powered from 5 volts. See Chapter 8, “PS/2 Mouse/Keyboard Port,” for additional information.
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R RS-232 Ports, VGA Port, and PS/2 Port UG230_Aa_02_021806 Figure A-2: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 2 www.xilinx.
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R Appendix A: Schematics Ethernet PHY, Magnetics, and RJ-11 Connector IC6 is an SMSC 10/100 Ethernet PHY, with its associated 25 MHz oscillator. The PHY requires an Ethernet MAC implemented within the FPGA. J19 is the RJ-11 Ethernet connector associated with the 10/100 Ethernet PHY. See Chapter 14, “10/100 Ethernet Physical Layer Interface,” for additional information. 138 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Ethernet PHY, Magnetics, and RJ-11 Connector UG230_Aa_03_021806 Figure A-3: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 4 www.xilinx.
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R Appendix A: Schematics Voltage Regulators IC7 is a Texas Instruments TPS75003 triple-output regulator. The regulator provides 1.2V to the FPGA’s VCCINT supply input, 2.5V to the FPGA’s VCCAUX supply input, and 3.3V to other components on the board and to the FPGA’s VCCO supply inputs on I/O Banks 0, 1, and 2. Jumpers JP6 and JP7 provide a means to measure current across the FPGA’s VCCAUX and VCCINT supplies respectively. IC8 is a Linear Technology LT3412 regulator, providing 2.
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R Voltage Regulators UG230_Aa_04_021806 Figure A-4: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 5 www.xilinx.
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R Appendix A: Schematics FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections IC10MISC represents the various FPGA configuration connections. IC11 is a 4 Mbit XCF04S Platform Flash PROM. Landing pads for a second XCF04S PROM is shown as IC13, although the second PROM is not mounted on the XC3S500E version of the board. Resistor R100 jumpers over the JTAG chain, bypassing the second XCF04S PROM. Jumper header J30 selects the FPGA’s configuration mode.
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R FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections UG230_Aa_05_021806 Figure A-5: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 6 www.xilinx.
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R Appendix A: Schematics FPGA I/O Banks 0 and 1, Oscillators IC10B0 represents the connections to I/O Bank 0 on the FPGA. The VCCO input to Bank 0 is 3.3V by default, but can be set to 2.5V using jumper JP9. IC10B1 represents the connections to I/O Bank 1 on the FPGA. IC17 is the 50 MHz clock oscillator. Chapter 3, “Clock Sources,” for additional information. IC16 is an 8-pin DIP socket to insert an alternate clock oscillator with a different frequency. 144 www.xilinx.
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R FPGA I/O Banks 0 and 1, Oscillators UG230_Aa_06_021806 Figure A-6: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 7 www.xilinx.
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R Appendix A: Schematics FPGA I/O Banks 2 and 3 IC10B2 represents the connections to I/O Bank 2 on the FPGA. Some of the I/O Bank 2 connections are used for FPGA configuration and are listed as IC10MISC. IC10B3 represents the connections to I/O Bank 3 on the FPGA. Bank 3 is dedicated to the DDR SDRAM interface and is consequently powered by 2.5V. See Chapter 13, “DDR SDRAM,” for additional information. 146 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R FPGA I/O Banks 2 and 3 UG230_Aa_07_021806 Figure A-7: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 8 www.xilinx.
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R Appendix A: Schematics Power Supply Decoupling IC10PWR represents the various voltage supply inputs to the FPGA and shows the power decoupling network. Jumper JP9 defines the voltage applied to VCCO on I/O Bank 0. The default setting is 3.3V. See “Voltage Control,” page 22 and “Voltage Supplies to the Connector,” page 116 for additional details. 148 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Power Supply Decoupling UG230_Aa_08_021806 Figure A-8: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 9 www.xilinx.
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R Appendix A: Schematics XC2C64A CoolRunner-II CPLD IC18 is a Xilinx XC2C64A CoolRunner™-II CPLD. The CPLD primarily provides additional flexibility when configuring the FPGA from parallel NOR Flash and during MultiBoot configurations. When the CPLD is loaded with the appropriate design, JP10 enables a watchdog timer in the CPLD used during fail-safe MultiBoot configurations. See Chapter 16, “XC2C64A CoolRunner-II CPLD,” for more information. 150 www.xilinx.
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R XC2C64A CoolRunner-II CPLD UG230_Aa_09_021806 Figure A-9: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 10 www.xilinx.
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R Appendix A: Schematics Linear Technology ADC and DAC IC19 is a Linear Technology LTC1407A-1 two-channel ADC. IC20 is a Linear Technology LTC6912 programmable pre-amplifier (AMP) to condition the analog inputs to the ADC. See Chapter 10, “Analog Capture Circuit,” for additional information. IC21 is a Linear Technology LTC2624 four-channel DAC. See Chapter 9, “Digital to Analog Converter (DAC),” for additional information. 152 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Linear Technology ADC and DAC UG230_Aa_10_021806 Figure A-10: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 11 www.xilinx.
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R Appendix A: Schematics Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM IC22 is a 128 Mbit (16 Mbyte) Intel StrataFlash parallel NOR Flash PROM. See Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM,” for additional information. IC23 is a 512 Mbit (64 Mbyte) Micron DDR SDRAM. See Chapter 13, “DDR SDRAM,” for additional information. 154 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM UG230_Aa_11_021806 Figure A-11: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 12 www.xilinx.
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R Appendix A: Schematics Buttons, Switches, Rotary Encoder, and Character LCD SW0, SW1, SW2, and SW3 are slide switches. Push-button switches W, E, S, and N are located around the ROT1 push-button switch/rotary encoder. LD0 through LD7 are discrete LEDs. See Chapter 2, “Switches, Buttons, and Knob,” for additional information. DISP1 is a 2x16 character LCD screen. See Chapter 5, “Character LCD Screen,” for additional information. 156 www.xilinx.
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R Buttons, Switches, Rotary Encoder, and Character LCD UG230_Aa_12_021806 Figure A-12: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 13 www.xilinx.
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R Appendix A: Schematics DDR SDRAM Series Termination and FX2 Connector Differential Termination Resistors R160 through R201 represent the series termination resistors for the DDR SDRAM. See Chapter 13, “DDR SDRAM,” for additional information. Resistors R202 through R210 are not loaded on the board. These landing pads provide optional connections for 100Ω differential termination resistors. See “Using Differential Inputs,” page 120 for additional information. 158 www.xilinx.
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R DDR SDRAM Series Termination and FX2 Connector Differential Termination UG230_Aa_13_021806 Figure A-13: Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.2) January 20, 2011 Schematic Sheet 14 www.xilinx.
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R Appendix A: Schematics 160 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide UG230 (v1.
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R Appendix B Example User Constraints File (UCF) ##################################################### ### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE ##################################################### # ==== Analog-to-Digital Converter (ADC) ==== # some connections shared with SPI Flash, DAC, ADC, and AMP NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW # ==== Programmable Gain Amplifier (AMP) ==== # some connections shared with SPI Flash, DAC, NET "AMP_CS" LOC = "N7" | IOSTANDARD =
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R Appendix B: Example User Constraints File (UCF) NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "E_MDIO" "E_RX_CLK" "E_RX_DV" "E_RXD<0>" "E_RXD<1>" "E_RXD<2>" "E_RXD<3>" "E_RXD<4>" "E_TX_CLK" "E_TX_EN" "E_TXD<0>" "E_TXD<1>" "E_TXD<2>" "E_TXD<3>" "E_TXD<4>" LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = "U5" "V3" "V2" "V8" "T11" "U11" "V14" "U14" "T7" "P15" "R11" "T15" "R5" "T5" "R6" | | | | | | | | | | | | | | | IOSTANDARD IOSTANDARD IOSTANDAR
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R NET NET NET NET NET NET NET NET NET NET NET NET NET NET "FX2_IO<27>" "FX2_IO<28>" "FX2_IO<29>" "FX2_IO<30>" "FX2_IO<31>" "FX2_IO<32>" "FX2_IO<33>" "FX2_IO<34>" "FX2_IP<35>" "FX2_IP<36>" "FX2_IP<37>" "FX2_IP<38>" "FX2_IO<39>" "FX2_IP<40>" LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = "A16" "B16" "E13" "C4" "B11" "A11" "A8" "G9" "D12" "C12" "A15" "B15" "C3" "C15" | | | | | | | | | | | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTAND
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R Appendix B: Example User Constraints File (UCF) NET "LED<6>" NET "LED<7>" LOC = "E9" LOC = "F9" | SLEW = SLOW | SLEW = SLOW | DRIVE = 8 | DRIVE = 8 # ==== Rotary Pushbutton Switch (ROT) ==== NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLUP ; | PULLUP ; | PULLDOWN ; | DRIVE = 8 ; | DRIVE = 8 ; # ==== PS/2 Mouse/Keyboard Port (PS2) ==== NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 NET "PS2_DATA"
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R NET "SD_LDM" NET "SD_LDQS" NET "SD_RAS" NET "SD_UDM" NET "SD_UDQS" NET "SD_WE" # Path to allow NET "SD_CK_FB" # Prohibit VREF CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT CONFIG PROHIBIT LOC = "J2" LOC = "L6" LOC = "C1" LOC = "J1" LOC = "G3" LOC = "D1" connection LOC = "B9" pins = D2; = G4; = J6; = L5; = R4; | IOSTANDARD = SSTL2_I ; | IOSTANDARD = SSTL2_I ; | IOSTANDARD = SSTL2_I ; | IOSTANDARD = SSTL2_I ; | IOSTANDARD = SSTL2_I ; | IOSTANDARD = SSTL2_I ; to top DCM connection | IOST
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R Appendix B: Example User Constraints File (UCF) NET "SF_OE" NET "SF_STS" NET "SF_WE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 LOC = "B18" | IOSTANDARD = LVCMOS33 ; LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; | SLEW = SLOW ; # ==== STMicro SPI serial Flash (SPI) ==== # some connections shared with SPI Flash, DAC, ADC, and AMP NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ; NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW NET "SPI_SCK" LOC = "U16" | IOSTAN