Altera High-Definition Multimedia Interface IP Core User Guide Subscribe Send Feedback UG-HDMI 2015.05.04 101 Innovation Drive San Jose, CA 95134 www.altera.
TOC-2 Contents HDMI Quick Reference.......................................................................................1-1 HDMI Overview.................................................................................................. 2-1 Resource Utilization.................................................................................................................................... 2-4 HDMI Getting Started.........................................................................................
TOC-3 HDMI Hardware Demonstration Requirements.................................................................................... 6-2 Transceiver and Clocking Configuration................................................................................................. 6-6 Software Process Flow............................................................................................................................... 6-10 Demonstration Walkthrough.........................................................
1 HDMI Quick Reference 2015.05.04 UG-HDMI Send Feedback Subscribe The Altera High-Definition Multimedia Interface (HDMI) IP core provides support for next-generation video display interface technology. Release Information Version 15.0 Release May 2015 Ordering Code IP-HDMI Product ID 0121 Vendor ID 6AF7 Core Features • Conforms to the High-Definition Multimedia Interface (HDMI) specification version 2.
2 HDMI Overview 2015.05.04 UG-HDMI Subscribe Send Feedback The Altera High-Definition Multimedia Interface (HDMI) IP core provides support for next generation video display interface technology.
2-2 UG-HDMI 2015.05.04 HDMI Overview Figure 2-1: Altera HDMI Block Diagram The figure below illustrates the blocks in the Altera HDMI IP core.
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2-4 UG-HDMI 2015.05.04 Resource Utilization Each data stream section is preceded with guard bands and pre-ambles. These allow for accurate synchro‐ nization with received data streams. Resource Utilization The resource utilization data indicates typical expected performance for the HDMI IP core device. Table 2-2: HDMI Data Rate The table lists the minimum and maximum data rates for FPGA fabric and standard RX/TX PCS, and PCS/PMA widths of 10, 20, and 40.
HDMI Getting Started 3 2015.05.04 UG-HDMI Subscribe Send Feedback This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with the HDMI IP core. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize the HDMI IP core to support a wide variety of applications.
3-2 OpenCore Plus IP Evaluation UG-HDMI 2015.05.04 OpenCore Plus IP Evaluation Altera's free OpenCore® Plus feature allows you to evaluate licensed MegaCore® IP cores in simulation and hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take your design to production. OpenCore Plus supports the following evaluations: • • • • Simulate the behavior of a licensed IP core in your system.
4 HDMI Source 2015.05.04 UG-HDMI Send Feedback Subscribe Source Functional Description The HDMI source core provides direct connection to the Transceiver Native PHY through a 10-bit, 20bit, or 40-bit parallel data path. Figure 4-1: HDMI Source Signal Flow Diagram The figure below shows the flow of the HDMI source signals. The figure shows the various clocking domains used within the core.
4-2 UG-HDMI 2015.05.04 Source TMDS/TERC4 Encoder The source core accepts video, audio, and auxiliary channel data streams. The core produces a TMDS/ TERC4 encoded data stream that would typically connect to the high-speed transceiver parallel data inputs. Central to the core is the TMDS/TERC4 encoder. The encoder processes either video or auxiliary data.
UG-HDMI 2015.05.04 Source Window of Opportunity Generator 4-3 Figure 4-3: Source Pixel Data Input Format RGB/YCbCr 4:4:4 The figure below shows the RGB color space pixel bit-field mappings. 24 bpp RGB/YCBCr444 (8 bpc) 30 bpp RGB/YCBCr444 (10 bpc) 36 bpp RGB/YCBCr444 (12 bpc) 48 bpp RGB/YCBCr444 (16 bpc) 47 32 31 16 15 vid_data[47:0] 0 Figure 4-4: Source Pixel Data Input Format YCbCr 4:2:2—12 bpc The figure below shows the YCbCr color space pixel bit-field mappings.
4-4 UG-HDMI 2015.05.04 Source Auxiliary Packet Encoder The output from the WOP generator is an aux_de signal propagated backwards through the auxiliary signal path to provide backpressure. Based on the HDMI Specification Ver.1.4b requirements, you cannot send more than 9 auxiliary (AUX) packets consecutively during a blanking region. The WOP generator deasserts the data enable line on every tenth AUX packet to comply with this requirement.
UG-HDMI 2015.05.04 Source Auxiliary Packet Generators 4-5 The encoder assumes the data valid input will remain asserted for the duration of a packet to complete. A packet is always 24 clocks (in 1-symbol mode), 12 clocks (in 2-symbol mode), or 6 clocks (in 4-symbol mode). The encoder creates a NULL auxiliary packet if it doesn't detect a start-of-packet at the beginning of a packet boundary.
4-6 UG-HDMI 2015.05.04 Source General Control Packet The core sends the auxiliary control packets on the active edge of the V-SYNC signal to ensure that the packets are sent once per field. Source General Control Packet Table 4-1: Source General Control Packet Input Fields The table below lists the bit-fields for the Source General Control Packet port.
UG-HDMI 2015.05.04 Source HDMI Vendor Specific InfoFrame (VSI) Bit-field Name 11:10 B Bar info data valid 12 A0 Active information present 14:13 Y RGB or YCbCr indicator 15 Reserved 19:16 R Active format aspect ratio 21:20 M Picture aspect ratio 23:22 C Colorimetry (for example: ITU BT.601, BT.
4-8 UG-HDMI 2015.05.04 Source Audio InfoFrame (AI) Table 4-3: HDMI Vendor Specific InfoFrame Bit-Fields The table below lists the bit-fields for VSI. The signal bundle is clocked by ls_clk.
UG-HDMI 2015.05.04 Source Audio Encoder Bit-field Name 15:12 CT Audio format type 17:16 SS Bits per audio sample 20:18 SF Sampling frequency 23:21 Reserved 31:24 CXT Audio format type of the audio stream 39:32 CA Speaker location allocation FL, FR 41:40 LFEPBL LFE playback level information, dB 42 Reserved Returns 0 46:43 LSV 47 DM_INH 48 4-9 Comment Returns 0 Level shift information, dB Down-mix inhibit flag Disables the core of the InfoFrame packets from inserting.
4-10 UG-HDMI 2015.05.04 Source Parameters Figure 4-8: Source Audio Encoder Timestamp Scheduler Auxiliary Packet Generator CTS, N Audio Data Port Multiplexer Default AI Override AI V-SYNC Auxiliary Packet Generator 1 DCFIFO Audio Input Audio Packetizer Audio Auxiliary Stream Auxiliary Packet Generator The Audio Timestamp InfoFrame packet contains the CTS and N values. You need to provide these values. The core schedules this packet to be sent every ms.
UG-HDMI 2015.05.04 Source Interfaces Parameter Value Support auxiliary Description Determines if auxiliary channel encoding is included. 0 = No AUX 1 = AUX Support deep color 4-11 0 = No deep color Determines if the core can encode deep color formats. 1 = Deep color To enable this parameter, you must also enable the Support auxiliary parameter. Note: This parameter is not supported for 15.0 release. The parameter always sets to 0.
4-12 UG-HDMI 2015.05.04 Source Interfaces Interface Port Type Clock Clock Domain N/A Port ls_clk Direction Input Description Link speed clock input. 8/8 (1x), 10/8 (1.25x), 12/8 (1.5x), or 16/8 (2x) times the vid_clk according to color depth. This signal connects to the transceiver output clock. Clock Clock N/A vid_clk Input Video data clock input.
UG-HDMI 2015.05.04 Source Interfaces Interface Port Type Conduit Clock Domain vid_clk Port vid_data[N*48-1:0] Direction Input HDMI Source Send Feedback Description Video 48-bit pixel data input port. • In 2 symbols per clock (N=2) mode, this port accepts two 48bit pixels per clock. • In 4 symbols per clock (N=4) mode, this port accepts four 48bit pixels per clock.
4-14 UG-HDMI 2015.05.04 Source Interfaces Interface Auxiliary Data Port Port Type Clock Domain Port Direction Description Conduit ls_clk aux_ready Output Auxiliary data channel valid output. Conduit ls_clk aux_valid Input Auxiliary data channel valid input. Conduit ls_clk aux_data[71:0] Input Auxiliary data channel data input. Conduit ls_clk aux_sop Input Auxiliary data channel start-ofpacket input. Conduit ls_clk aux_eop Input Auxiliary data channel end-ofpacket input.
UG-HDMI 2015.05.04 Source Clock Tree Interface Audio Port Port Type Clock Domain Port Direction 4-15 Description Conduit audio_clk audio_CTS[21:0] Input Audio CTS value input. Conduit audio_clk audio_N[21:0] Input Audio N value input. Conduit audio_clk Input Audio data input. Conduit audio_clk audio_ data[32*(2+6*M)1:0] audio_de[2+6*M1:0] M is 1 when you enable support for 8-channel audio. Otherwise it is 0. Input Audio data valid input.
4-16 UG-HDMI 2015.05.04 Source Clock Tree Figure 4-9: Source Clock Tree The figure shows how the different clocks connect in the source core. Transceiver Block HDMI Source Core ls_clk vid_clk WRCLK Pixel Data RDCLK Resampler FIFO WRCLK RDCLK Sync HSSI[0] Channel[0] WRCLK RDCLK Sync HSSI[1] Channel[1] Sync HSSI[2] Channel[2] WRCLK RDCLK Sync HSSI[3] TMDS Clock Switch Transceiver PLL TMDS (TERC4) Encoder WRCLK RDCLK AUX Data GPLL vid_clk x1.0 x1.25 x1.5 x2.
HDMI Sink 5 2015.05.04 UG-HDMI Send Feedback Subscribe Sink Functional Description The HDMI sink core provides direct connection to the Transceiver Native PHY through a 10-bit, 20-bit, or 40-bit parallel data path. Figure 5-1: HDMI Sink Signal Flow Diagram The figure below shows the flow of the HDMI sink signals. The figure shows the various clocking domains used within the core.
5-2 Sink Channel Word Alignment and Deskew UG-HDMI 2015.05.04 Sink Channel Word Alignment and Deskew The input stage of the sink is responsible for synchronizing the incoming parallel data channels correctly. The synchronization is split to two stages: word alignment and channel deskew. Word alignment • Correctly aligns the incoming parallel data to word boundaries using bit-slip technique.
UG-HDMI 2015.05.04 Sink TMDS/TERC4 Decoder 5-3 Figure 5-2: Channel Deskew DCFIFO Arrangement The figure below shows the signal flow diagram of the deskew logic.
5-4 UG-HDMI 2015.05.04 Sink Video Resampler Sink Video Resampler The video resampler consists of a gearbox and a dual-clock FIFO (DCFIFO). The gearbox converts 8 bit-per-second (bps) data to 8-, 10-, 12- or 16-bps data based on the current color depth. The GCP conveys the color depth information.
UG-HDMI 2015.05.04 Sink Auxiliary Packet Capture 5-5 Figure 5-4: Auxiliary Data Stream Signal The figure below shows the relationship between the data bit-field and its clock cycle based on 1-, 2-, or 4symbol per clock mode.
5-6 UG-HDMI 2015.05.04 Sink General Control Packet Sink General Control Packet Table 5-1: General Control Packet Input Fields Bit Field Name Comment CD3 CD2 CD1 CD0 0 0 0 0 Color depth not indicated 0 0 0 1 Reserved 0 0 1 0 Reserved 0 0 1 1 Reserved 0 1 0 0 24 bpp 0 1 0 1 30 bpp (2) 0 1 1 0 36 bpp (2) 0 1 1 1 48 bpp (2) 1 1 1 1 Reserved Color Depth (CD) gcp[3:0] gcp[4] Set_ AVMUTE Refer to HDMI Specification Ver.1.
UG-HDMI 2015.05.04 Sink HDMI Vendor Specific InfoFrame (VSI) Bit-field Name 19:16 R Active format aspect ratio 21:20 M Picture aspect ratio 23:22 C Colorimetry (for example: ITU BT.601, BT.
5-8 UG-HDMI 2015.05.04 Sink Auxiliary Data Port Bit-field Name 60:58 3D_Ext_Data Comment 3D extended data Sink Auxiliary Data Port The auxiliary port is attached to external memory. This port allows you to write packets to memory for use outside the HDMI core. The core calculates the address for the data port using the header byte of the received packet. The core writes packet types 0–15 into a contiguous memory region.
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UG-HDMI 2015.05.04 Sink Audio Decoding 5-11 MPEG Source InfoFrame 61 PB24 PB23 PB17 PB16 PB10 PB9 PB3 PB2 HB1 62 PB26 PB25 PB19 PB18 PB12 PB11 PB5 PB4 HB2 63 BCH3 PB27 BCH2 PB20 BCH1 PB13 BCH0 PB6 HBCH0 Sink Audio Decoding The sink core sends the audio data using auxiliary packets. You can use three packet types in transporting audio: Audio InfoFrame, Audio Timestamp, and Audio Sample Data.
5-12 UG-HDMI 2015.05.04 Sink Interfaces Parameter Direction Value Transmitter = Source Description Select HDMI sink. Receiver = Sink Symbols per clock 1, 2, or 4 symbols per clock Determines how many TMDS symbols and pixels are processed per clock.
UG-HDMI 2015.05.04 Sink Interfaces 5-13 Table 5-6: Sink Interfaces N is the number of symbols per clock. Interface Reset Port Type Reset Clock Domain N/A Port reset Direction Input Description Main asynchro‐ nous reset input. Note: Resetting the input will reset the SCDC register. Clock Clock N/A ls_clk[2:0] Input Link speed clock input. These clocks correspond to the in_r, in_g, and in_b TMDS encoded data inputs. Clock N/A vid_clk Input Video data clock input.
5-14 UG-HDMI 2015.05.04 Sink Interfaces Interface Port Type Conduit Clock Domain vid_clk Port vid_data[N*48-1:0] Direction Output Description Video 48-bit pixel data output port. In 2 symbols per clock (N=2) mode, this port produces two 48-bit pixels per clock. In 4 symbols per clock (N=4) mode, this port produces four 48-bit pixels per clock. Video Data Port Conduit vid_clk vid_de[N-1:0] Output Video data enable output that indicates active picture region.
UG-HDMI 2015.05.04 Sink Interfaces Interface TMDS Data Port Port Type Clock Domain Port Direction 5-15 Description Conduit ls_clk[0] in_b[N*10-1:0] Input TMDS encoded blue channel input. Conduit ls_clk[1] in_r[N*10-1:0] Input TMDS encoded red channel input. Conduit ls_clk[2] in_g[N*10-1:0] Input TMDS encoded green channel input. Conduit ls_clk[2:0] in_lock[2:0] Input Ready signal from the transceiver reset controller that indicates the transceivers are locked.
5-16 UG-HDMI 2015.05.04 Sink Interfaces Interface Port Type Clock Domain Port Direction Description Conduit ls_clk[0] audio_CTS[21:0] Output Audio CTS value output. Conduit ls_clk[0] audio_N[21:0] Output Audio N value output. Conduit ls_clk[0] Output Audio data output. audio_ data[32*(2+6*M)1:0] M is 1 when you enable support for 8-channel audio. Otherwise it is 0. Audio Port Conduit ls_clk[0] audio_valid[2+6*M1:0] Output Audio data valid output.
UG-HDMI 2015.05.04 Avalon-MM SCDC Management Interface Interface Auxiliary Control Port Port Type Clock Domain Port Direction 5-17 Description Conduit ls_clk[0] gcp[5:0] Output General Control Packet output. Conduit ls_clk[0] gcp_Set_AVMute Output General Control Packet mute output. Conduit ls_clk[0] gcp_Clear_AVMute Output General Control Packet clear output. Conduit ls_clk[0] info_avi[111:0] Output Auxiliary Video Information InfoFrame output.
5-18 UG-HDMI 2015.05.04 Sink Clock Tree • • • • 8-bpp—link speed clock divided by 1 10-bpp—link speed clock divided by 1.25 12-bpp—link speed clock divided by 1.5 16-bpp—link speed clock divided by 2 For HDMI sink, you need to instantiate 3 receiver channels to receive data. Figure 5-7: Sink Clock Tree The figure shows how the different clocks can be selected for the sink core.
6 HDMI Hardware Demonstration 2015.05.04 UG-HDMI Subscribe Send Feedback The Altera High-Definition Multimedia Interface (HDMI) hardware demonstration allows you to evaluate the functionality of the HDMI IP core and provides a starting point for you to create your own design. The demonstration runs on both Arria V GX starter board and Stratix V GX development board. • For HDMI 2.0 design, use Bitec HDMI 2.0 HSMC daughter card revision 1. • For HDMI 1.4b design, use Bitec HDMI 1.
6-2 UG-HDMI 2015.05.04 HDMI Hardware Demonstration Requirements Figure 6-1: HDMI Hardware Demonstration Block Diagram The figure below shows a high level block diagram of the demonstration.
UG-HDMI 2015.05.04 HDMI Hardware Demonstration Requirements 6-3 Figure 6-2: Interface Signal Connections (Bitec HDMI 1.
6-4 UG-HDMI 2015.05.04 HDMI Hardware Demonstration Requirements Figure 6-3: Adaptive Cable Equalizer and Level Shifter (Bitec HDMI 1.
UG-HDMI 2015.05.04 HDMI Hardware Demonstration Requirements 6-5 Figure 6-4: Interface Signal Connections (Bitec HDMI 2.
6-6 Transceiver and Clocking Configuration UG-HDMI 2015.05.04 Figure 6-5: Adaptive Cable Equalizer and Level Shifter (Bitec HDMI 2.0 HSMC) Related Information • Arria V GX Starter Kit User Guide • Stratix V GX FPGA Development Kit User Guide Transceiver and Clocking Configuration The Arria V demonstration uses 2 symbols per clock for HDMI 1.4b design and 4 symbols per clock for HDMI 2.0 design. The Stratix V demonstration uses 2 symbols per clock for HDMI 1.4b and 2.0 designs.
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UG-HDMI 2015.05.04 Transceiver and Clocking Configuration Signal Direction 6-9 Connection Receiver Interfaces rx_serial_data Input Connect to the HDMI TMDS data channel. • Bit 0: Blue channel • Bit 1: Green channel • Bit 2: Red channel rx_set_locktodata Input Always assign to 1. rx_set_locktoref Input • Assert for oversampling cases • Deassert for non-oversampling cases rx_is_lockedtoref Output Connect to the transceiver reset controller.
6-10 UG-HDMI 2015.05.04 Software Process Flow Transmitter Interfaces tx_std_coreclkin Input Connect to the clock that previously clocks the TX PCS and core logic. This port is normally connected to the rx_std_ clkout signal. tx_std_clkout Output Connect to the tx_std_coreclkin signal in the transmitter. tx_cal_busy Output Connect to the transceiver reset controller.
UG-HDMI 2015.05.04 Software Process Flow 6-11 Figure 6-6: Software Process for PLL, Transmitter, or TX PLL Reconfiguration The figure below shows the software process flow. Note: The Clocked Video Input, Clocked Video Output, and Frame Buffer IP cores are only used in the HDMI 1.
6-12 UG-HDMI 2015.05.04 Demonstration Walkthrough Demonstration Walkthrough Setting up and running the HDMI hardware demonstration consists of four stages. You can use the Altera-provided scripts to automate these stages. 1. 2. 3. 4. Set up the hardware. Copy the design files to your working directory. Build and download the design. Power up the HDMI monitor and view the results. Set Up the Hardware The first stage of the demonstration is to set up the hardware.
UG-HDMI 2015.05.04 View the Results 6-13 This script executes the following commands: • • • • • • • Generate IP catalog files Generate the Qsys system Create a Quartus II project Create a software work space and build it Compile the Quartus II project Run Analysis & Synthesis to generate a post-map netlist for DDR assignments Perform a full compile Note: If you are a Linux user, you will get a message cygpath: command not found.
7 HDMI Simulation Example 2015.05.04 UG-HDMI Subscribe Send Feedback The Altera HDMI simulation example evaluates the functionality of the HDMI IP core and provides a starting point for you to create your own simulation. This simulation example targets the Modelsim SE simulator. The simulation covers the following core features: • • • • IEC-60958 audio format Standard H/V/DE/RGB input video format Support for 4 symbols per clock Support for HDMI 2.
7-2 UG-HDMI 2015.05.04 Simulation Walkthrough The testbench implements CRC checking on the input and output video. The testbench checks the CRC value of the transmitted data against the CRC calculated in the received video data. The testbench performs the checking after detecting 4 stable V-SYNC signals from the receiver. Simulation Walkthrough Setting up and running the HDMI simulation example consists of two steps. 1.
UG-HDMI 2015.05.04 Simulation Walkthrough 7-3 Command Generate the simulation files for the HDMI cores. • ip-generate --project-directory=./ --componentfile=./hdmi_rx_single.qsys --output-directory=./ hdmi_rx_single/sim/ --file-set=SIM_VERILOG -report-file=sopcinfo:./hdmi_rx_single.sopcinfo -report-file=html:./hdmi_rx_single.html -report-file=spd:./hdmi_rx_single/sim/hdmi_rx_ single.spd --report-file=qip:./hdmi_rx_single/ sim/hdmi_rx_single.qip • ip-generate --project-directory=./ --componentfile=.
7-4 Simulation Walkthrough UG-HDMI 2015.05.04 Command Compile and simulate the design in the ModelSim software.
A Additional Information for High-Definition Multimedia Interface User Guide 2015.05.04 UG-HDMI Subscribe Send Feedback Document Revision History for HDMI User Guide Date May 2015 Version 2015.05.04 Changes • Updated the HDMI IP core resource utilization table with 15.0 information. • Added information about 4 symbols per clock mode. • Added information about Status and Control Data Channel (SCDC) for HDMI specification version 2.0.
