User Guide

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2. SGH-E100 Circuit Description
2-1
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Ⅰ. SGH-E100 RF Circuit Description
1. RX PART
1.1 ASM(MODULE1)
→
Switching Tx, Rx path for GSM900, DCS1800 by logic controlling.
1.2 ASM Control Logic (U206, U208)
→
Truth Table
VC_1 VC_2
GSM Tx Mode H L
DCS Tx Mode L H
GSM Rx Mode L L
DCS Rx Mode L L
1.3 FILTER
To convert Electromagnetic Field Wave to Acoustic Wave and then pass the specific frequency
band.
- GSM FILTER (F100)
→
For filtering the frequency band between 925 ~ 960 MHz
- DCS FILTER (F102)
→
For filtering the frequency band 1805 and 1880 MHz.
1.4 TC-VCXO (U101)
To generate the 26MHz reference clock to drive the logic and RF.
After additional process, the reference clock applies to the U100 Rx IQ demodulator and Tx
IQ modulator.
The oscillator for RX IQ demodulator and Tx modulator are controlled by serial data to select
channel and use fast lock mode for GPRS high class operation.
1.5 UAA3536(U100)
This chip integrates two differential-input LNAs.
The GSM input supports the E-GSM, DCS input supports the DCS1800. The LNA inputs are
matched to the 200 ohm differential output SAW filters through eternal LC matching network.
Image-reject mixer downconverts the RF signal to a 100 KHz intermediate frequency(IF) with
the RFLO from VOU1810 voltage-controlled oscillator. The RFLO frequency is between 1801 ~
1921 MHz.
The Mixer output is amplified with an analog programmable gain amplifier(PGA), which is
controlled by AGAIN.
The quadrature IF signal is digitized with high resolution A/D converts (ADC).