Specifications

96 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
Table 8-4. USB Channel Routing Guidelines
Parameter Routing Guidelines Figure
Signal Group USB[1:0]P_P, and USB[1:0]P_N
Reference Plane Ground Referenced,
Ground vias are required when signal net has layer transition.
Layer Assignment Top layer or bottom layer (Micro Strip)
Trace Impedance (Z0) 90 Ω +/-10% (differential)
nominal Trace width (W) 4 mil –micro strip (which is preferred) Figure 8-6
Nominal Trace Spacing Intra-pair Trace Spacing (fixed):4.0 mils – micro strip
Inter-pair spacing (minimum): 20 mils
To Other signal spacing (minimum): 20 mils
Figure 8-6
nominal Trace Length Keep all lengths as short as possible.
Length TL2 must be as short as possible to keep the choke as
close to the connector as possible.
Back Panel: TLT1=TL1+TL2 +TL3 --- 2” to 8”.
FEB: TLT2=TL1+TL2+TL41+TL42 --- up to 20”
while TL1 +TL2 --- 2” to 6”
Figure 8-4
Figure 8-5
Length Matching requirements Length matching over TLT within a differential is within 60 mils or
less.
Breakout 4 mils width with 4 mils spacing for maximum length of 500 mils,
minimize this length.
Breakout length: 0.1” to 1.0” included in TL1.
Vias Maximum 4 vias in each net for routing partly on bottom layer.
Ground vias are required when signal net has layer transition.