Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 9
Platform Design Guide
Intel Confidential
Figure 8-7. USBRBIAS/USBRBIASN Connection ......................................................................................97
Figure 8-8. Design Example........................................................................................................................98
Figure 8-9. GBE Interface Clock Signal Design Example.........................................................................100
Figure 8-10. GBE TX Interface (except GBE_TXCLK) .............................................................................100
Figure 8-11. GBE_TXCLK.........................................................................................................................100
Figure 8-12. GBE_TXCTL.........................................................................................................................101
Figure 8-13. GBE_REFCLK......................................................................................................................101
Figure 8-14. GBE_RXDATA<0~3> and GBE_RXCLK ............................................................................. 102
Figure 8-15. Expansion Bus Implementation Showing 26-bit Addressing Example.................................103
Figure 8-16. Expansion Bus Topology for EXP_CS[3:0]B........................................................................ 104
Figure 8-17. Expansion Bus Address ADDR<0, 2-15>, EXP_ALE and EXP_IO_WRB Topology ...........105
Figure 8-18. Data Bus DA<0-7> Topology................................................................................................106
Figure 8-19. Expansion Bus Topology for EXP_DB<0-7>, EXP_RDB, EXP_WRB and EXP_IO_RDB
@25MHz ............................................................................................................................................107
Figure 8-20. NAND Flash Controller .........................................................................................................108
Figure 8-21. I2C Bus Interconnects Topology ..........................................................................................114
Figure 8-22. UART0_RXD signal Topology..............................................................................................116
Figure 8-23. UART0_DSRB signal Topology............................................................................................117
Figure 8-24. GPIO Interface Topology...................................................................................................... 119
Figure 8-25. SPI SPI_MISO signal Topology............................................................................................ 121
Figure 8-26. SPI_MOSI and SPI_SCK signal Topology ........................................................................... 122
Figure 8-27. SPI_SS signal Topology....................................................................................................... 123
Figure 8-28. SC Signal Topology..............................................................................................................125
Figure 9-1. HDVCAP Block Diagram ........................................................................................................ 126
Figure 9-2. HDVCAP Signal Topology With NOR Boot ............................................................................128
Figure 9-3. HDVCAP Signal Topology With NAND Boot.......................................................................... 129
Figure 10-1. Clock Diagram Example. ......................................................................................................130
Figure 10-2. Intel Platform Clock Diagram Example.................................................................................131
Figure 10-3. CK505 Reference Clock Topology .......................................................................................132
Figure 10-4. IDT6V49061 HDMI Reference Clock Topology.................................................................... 134
Figure 10-5. IDT6V49061 Audio and VDC CLK Topology........................................................................135
Figure 10-6. Audio_clk Signal Topology ...................................................................................................136