Specifications

Ref# 420826 Intel
®
Atom™ processor CE4100 85
Platform Design Guide
Intel Confidential
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7.1 Overview
The Intel
®
Atom™ processor CE4100 supports one 7.1 I
2
S output, one stereo I
2
S output,
and one S/PDIF output. All of these outputs can be functioning simultaneously. On the input
side, it will support one stereo I
2
S input.
7.2 I
2
S Audio Input Interface
The I
2
S audio capture port provides the bit clock and the WS sample rate clock derived from
the Fs*768=36.864 MHz I
2
S system clock (AUDIO_CLOCK). This interface includes
I2S_BCK_IN, I2S_LRW_IN and I2S_SDATA_IN. The AUDIO_CLOCK is generated by the
audio PLL and supplied to the I
2
S interface clock input. The audio demodulator/decoder or
ADC must supply data synchronously with this clock for proper system operation.
Figure 7-1. I
2
S Audio Input Interconnects Topology
I
2
S signals should be routed over unbroken reference planes, and should have no more than three
vias per device on average. Length matching is not required for the I2S_BCK_IN, I2S_LRWS_IN,
I2S_SDATA_IN signals.
Table 7-1. I
2
S Audio Input Interconnects
Traces Layer Min Length
Max
Length
Trace:
Width/Spacing
Spacing from other
signals
W_TL1
break out
0.1” 0.5” 4 mils >=8 mils
W_TL2
Micro strip
0.5” 9” 4 mils >=8 mils
Notes:
• All trace impedance required to be 55 Ω +/- 10%.
• All signals prefer to reference to ground plane and routed over a continuous plane.
• Simulation data based on Cin = 10pF (no IBIS models).