Specifications

84 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
6.3.1 TS Interface Routing Topology Example
The topology shown in Figure 6-15 is the same for the input transport stream clock,
transport stream data [D0:D1], and the associated control signals. The trace widths
provided here assume all the trace impedances are 55 Ω +/- 10% (4 mile trace).
Figure 6-15. TS Interface Routing Topologies
Traces Description Layer
Min
Length
Max
Length
Trace
Width
Spacing
TL1 3384 breakout Micro strip 0.1” 0.5” 4 Mils >=10Mils
TL2 Lead in Micro strip 1.0” 8.0” 4 Mils >=10 Mils
TL3
Intel
®
Atom™ processor
CE4100 Break out
Micro strip 0.1” 0.5” 4 Mils >=14Mils
Routing Guidelines
• All trace impedance required to be 55 Ω +/- 10%.
• Trace widths provided here are targeted only for 55 Ω.
• TS interface are preferred to have Ground referenced.
• Minimize the vias to be used.
• Match trace length of all data lines within +/-0.25” to clock line in “TL1+TL2+TL3”