Specifications

8 Intel
®
Atom™ processor CE4100 Ref# 420826
Platform Design Guide
Intel Confidential
List of Figures
Figure 2-1. Platform Overview ....................................................................................................................20
Figure 3-1. Recommended 6-layer PCB Stack-up Dimensions..................................................................23
Figure 3-2. Recommended 4-layer PCB Stack-up Dimensions..................................................................24
Figure 4-1. Power on sequence.................................................................................................................. 32
Figure 5-1. DDR3 Memory Clock Topology ................................................................................................46
Figure 5-2. DDR3 Address, Command and Control Topology with Two Loads ......................................... 48
Figure 5-3. DDR3 DQ/DM/DQS Topology ..................................................................................................49
Figure 5-4. DDR3 Memory Clock Topology ................................................................................................50
Figure 5-5. DDR3 Address, Command and Control Topology with Four Loads.........................................52
Figure 5-6. DDR3 DQ/DM/DQS Topology ..................................................................................................54
Figure 5-7. DDR2 Memory Clock Topology ................................................................................................55
Figure 5-8. DDR2 Address, Command and Control Topology with Two Loads ......................................... 57
Figure 5-9. DDR2 DQ/DM/DQS Topology ..................................................................................................58
Figure 5-10. DDR2 Memory Clock Topology..............................................................................................60
Figure 5-11. DDR2 Address, Command and Control Topology with Four Loads....................................... 62
Figure 5-12. DDR2 DQ/DM/DQS Topology ................................................................................................64
Figure 5-13. DDR Vref Circuit Example ......................................................................................................65
Figure 5-14. RCOMPPD Connection ..........................................................................................................66
Figure 5-15. RCOMPPU Connection ..........................................................................................................66
Figure 6-1. VDAC application Model 1: VDAC with Integrated Filter/Amplifier........................................... 69
Figure 6-2. VDAC application Model 2: VDAC with Discrete Filter............................................................. 70
Figure 6-3. VBG_EXTR_VDAC Resistor Design........................................................................................71
Figure 6-4. VBG_EXTR_VDAC Connection ...............................................................................................72
Figure 6-5. Illustration of Video DAC Trace Spacing ..................................................................................72
Figure 6-6. Design Example One................................................................................................................ 73
Figure 6-7. Design Example Two................................................................................................................ 73
Figure 6-8. HDMI Interface Diagram...........................................................................................................74
Figure 6-9. 4-pair HDMI channel Topology................................................................................................. 75
Figure 6-10. Using an IP4777CZ38 ESD Device Example – 6+ Layer Stack-up. ...................................... 78
Figure 6-11. Using an IP4777CZ38 ESD Device Example – 4 Layer Stack-up. ........................................79
Figure 6-12. Using a CM2030 or TPD12S521 ESD Device Example – 6+ Layer Stack-up....................... 81
Figure 6-13. Using a CM2030 or TPD12S521 ESD Device Example – 4 Layer Stack-up.........................82
Figure 6-14. HDMI TMDS Topology ...........................................................................................................83
Figure 6-15. TS Interface Routing Topologies ............................................................................................84
Figure 7-1. I
2
S Audio Input Interconnects Topology ...................................................................................85
Figure 7-2. I
2
S Audio Output Interconnects Topology ................................................................................ 86
Figure 7-3. S/PDIF Audio Output Interconnects Topology ......................................................................... 87
Figure 8-1. Serial ATA Topology.................................................................................................................89
Figure 8-2. Illustration of Serial ATA Trace Spacing................................................................................... 90
Figure 8-3. SATARBIAS Connection ..........................................................................................................92
Figure 8-4. USB2.0 Topology for Back Panel.............................................................................................94
Figure 8-5. USB2.0 Topology for Front END Board (FEB) .........................................................................94
Figure 8-6. Recommended USB Trace Spacing ........................................................................................95